URL
https://opencores.org/ocsvn/usb_fpga_1_11/usb_fpga_1_11/trunk
Subversion Repositories usb_fpga_1_11
[/] [usb_fpga_1_11/] [trunk/] [examples/] [usb-fpga-2.01/] [2.01b/] [intraffic/] [fpga/] [intraffic.ucf] - Rev 9
Compare with Previous | Blame | View Log
NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK" LOC = "T8" | IOSTANDARD = LVCMOS33 ;
NET "RESET" LOC = "R11" | IOSTANDARD = LVCMOS33 ; # PA0
NET "CONT" LOC = "T10" | IOSTANDARD = LVCMOS33 ; # PA1
NET "SLOE" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
NET "FIFOADR0" LOC = "T11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
NET "FIFOADR1" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
NET "PKTEND" LOC = "T5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6
#NET "PA<7>" LOC = "R3" | IOSTANDARD = LVCMOS33 ; # PA7/FLAGD/SLCS#
NET "FD<0>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; # PB0/FD0
NET "FD<1>" LOC = "R9" | IOSTANDARD = LVCMOS33 ; # PB1/FD1
NET "FD<2>" LOC = "P9" | IOSTANDARD = LVCMOS33 ; # PB2/FD2
NET "FD<3>" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # PB3/FD3
NET "FD<4>" LOC = "M10" | IOSTANDARD = LVCMOS33 ; # PB4/FD4
NET "FD<5>" LOC = "P11" | IOSTANDARD = LVCMOS33 ; # PB5/FD5
NET "FD<6>" LOC = "M11" | IOSTANDARD = LVCMOS33 ; # PB6/FD6
NET "FD<7>" LOC = "M12" | IOSTANDARD = LVCMOS33 ; # PB7/FD7
NET "FD<8>" LOC = "P8" | IOSTANDARD = LVCMOS33 ; # PD0/FD8
NET "FD<9>" LOC = "M7" | IOSTANDARD = LVCMOS33 ; # PD1/FD9
NET "FD<10>" LOC = "P7" | IOSTANDARD = LVCMOS33 ; # PD2/FD10
NET "FD<11>" LOC = "R7" | IOSTANDARD = LVCMOS33 ; # PD3/FD11
NET "FD<12>" LOC = "M6" | IOSTANDARD = LVCMOS33 ; # PD4/FD12
NET "FD<13>" LOC = "N6" | IOSTANDARD = LVCMOS33 ; # PD5/FD13
NET "FD<14>" LOC = "P6" | IOSTANDARD = LVCMOS33 ; # PD6/FD14
NET "FD<15>" LOC = "T6" | IOSTANDARD = LVCMOS33 ; # PD7/FD15
NET "FLAGB" LOC = "M9" | IOSTANDARD = LVCMOS33 ; # CTL1/FLAGB
NET "SLRD" LOC = "T4" | IOSTANDARD = LVCMOS33 ; # RDY0/SLRD
NET "SLWR" LOC = "P4" | IOSTANDARD = LVCMOS33 ; # RDY1/SLWR