URL
https://opencores.org/ocsvn/usb_fpga_1_15/usb_fpga_1_15/trunk
Subversion Repositories usb_fpga_1_15
[/] [usb_fpga_1_15/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15d/] [intraffic/] [fpga/] [intraffic.ucf] - Rev 2
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# NET "CLK" TNM_NET = "FXCLK";
# TIMESPEC "TS_CLK" = PERIOD "FXCLK" 20.83333 ns HIGH 50 %;
# NET "CLK" LOC = "L22" | IOSTANDARD = LVCMOS33 ;
NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20 ns HIGH 50 %;
NET "IFCLK" LOC = "K20" | IOSTANDARD = LVCMOS33 ;
# TIMESPEC "TS_CLK_IFCLK" = FROM "CLK" TO "IFCLK" 3ns DATAPATHONLY;
# TIMESPEC "TS_IFCLK_CLK" = FROM "IFCLK" TO "CLK" 3ns DATAPATHONLY;
NET "SLOE" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA2
NET "FIFOADR0" LOC = "W17" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA4
NET "FIFOADR1" LOC = "Y18" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA5
NET "PKTEND" LOC = "AB5" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ; # PA6
NET "RESET" LOC = "AB17" | IOSTANDARD = LVCMOS33 ; # PA7
NET "CONT" LOC = "G20" | IOSTANDARD = LVCMOS33 ; # PA3
NET "fd<0>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
NET "fd<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
NET "fd<2>" LOC = "W13" | IOSTANDARD = LVCMOS33 ;
NET "fd<3>" LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
NET "fd<4>" LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
NET "fd<5>" LOC = "W6" | IOSTANDARD = LVCMOS33 ;
NET "fd<6>" LOC = "Y6" | IOSTANDARD = LVCMOS33 ;
NET "fd<7>" LOC = "Y9" | IOSTANDARD = LVCMOS33 ;
NET "fd<8>" LOC = "V21" | IOSTANDARD = LVCMOS33 ;
NET "fd<9>" LOC = "V22" | IOSTANDARD = LVCMOS33 ;
NET "fd<10>" LOC = "U20" | IOSTANDARD = LVCMOS33 ;
NET "fd<11>" LOC = "U22" | IOSTANDARD = LVCMOS33 ;
NET "fd<12>" LOC = "R20" | IOSTANDARD = LVCMOS33 ;
NET "fd<13>" LOC = "R22" | IOSTANDARD = LVCMOS33 ;
NET "fd<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
NET "fd<15>" LOC = "P19" | IOSTANDARD = LVCMOS33 ;
NET "FLAGB" LOC = "F19" | IOSTANDARD = LVCMOS33 ;
NET "SLRD" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;
NET "SLWR" LOC = "M22" | IOSTANDARD = LVCMOS33 | DRIVE = 12 ;