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https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Subversion Repositories usb_fpga_1_2
[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.11/] [1.11c/] [memtest/] [fpga/] [ipcore_dir/] [mem0.xco] - Rev 7
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Tue Oct 5 21:28:57 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ftg256
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG family Xilinx,_Inc. 3.5
# END Select
# BEGIN Parameters
CSET component_name=mem0
CSET xml_input_file=./mem0/user_design/mig.prj
# END Parameters
GENERATE
# CRC: 43347ccc