URL
https://opencores.org/ocsvn/usb_fpga_1_2/usb_fpga_1_2/trunk
Subversion Repositories usb_fpga_1_2
[/] [usb_fpga_1_2/] [trunk/] [examples/] [usb-fpga-1.15/] [1.15d/] [memtest/] [fpga/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [memc3_infrastructure.vhd.diff] - Rev 8
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--- memc3_infrastructure.orig.vhd 2010-08-20 11:42:53.000000000 +0200
+++ memc3_infrastructure.vhd 2010-08-20 11:48:07.000000000 +0200
@@ -122,7 +122,6 @@
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
- signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
@@ -135,7 +134,6 @@
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
- attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
@@ -144,33 +142,6 @@
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
- diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
- --***********************************************************************
- -- Differential input clock input buffers
- --***********************************************************************
- u_ibufg_sys_clk : IBUFGDS
- generic map (
- DIFF_TERM => TRUE
- )
- port map (
- I => sys_clk_p,
- IB => sys_clk_n,
- O => sys_clk_ibufg
- );
- end generate;
-
-
- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
- --***********************************************************************
- -- SINGLE_ENDED input clock input buffers
- --***********************************************************************
- u_ibufg_sys_clk : IBUFG
- port map (
- I => sys_clk,
- O => sys_clk_ibufg
- );
- end generate;
-
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
@@ -209,7 +180,7 @@
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
- CLKIN1 => sys_clk_ibufg,
+ CLKIN1 => sys_clk,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',