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https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [_xmsgs/] [pn_parser.xmsgs] - Rev 2
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
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<!-- behavior or data corruption. It is strongly advised that -->
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<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/infrastructure.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/iodrp_controller.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/iodrp_mcb_controller.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/mcb_raw_wrapper.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mcb_controller/mcb_ui_top.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/mem0.v" into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.04b/ipcore_dir/mem0/user_design/rtl/memc_wrapper.v" into library work</arg>
</msg>
</messages>