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https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [infrastructure.v.diff] - Rev 2
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--- infrastructure.orig.v 2014-05-22 14:50:42.000000000 +0200 +++ infrastructure.v 2014-06-02 14:43:45.000000000 +0200 @@ -123,44 +123,11 @@ wire sys_rst; wire bufpll_mcb_locked; - (* KEEP = "TRUE" *) wire sys_clk_ibufg; assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i; assign clk0 = clk0_bufg; assign pll_lock = bufpll_mcb_locked; - generate - if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk - - //*********************************************************************** - // Differential input clock input buffers - //*********************************************************************** - - IBUFGDS # - ( - .DIFF_TERM ("TRUE") - ) - u_ibufg_sys_clk - ( - .I (sys_clk_p), - .IB (sys_clk_n), - .O (sys_clk_ibufg) - ); - - end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk - - //*********************************************************************** - // SINGLE_ENDED input clock input buffers - //*********************************************************************** - - IBUFG u_ibufg_sys_clk - ( - .I (sys_clk), - .O (sys_clk_ibufg) - ); - end - endgenerate - //*************************************************************************** // Global clock generation and distribution //*************************************************************************** @@ -199,7 +166,7 @@ ( .CLKFBIN (clkfbout_clkfbin), .CLKINSEL (1'b1), - .CLKIN1 (sys_clk_ibufg), + .CLKIN1 (sys_clk), .CLKIN2 (1'b0), .DADDR (5'b0), .DCLK (1'b0),