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Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.18/] [memfifo.srcs/] [sources_1/] [ip/] [mig_7series_0/] [mig_7series_0/] [datasheet.txt] - Rev 2
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Vivado Project Options:
Target Device : xc7a200t-fbg484
Speed Grade : -2
HDL : verilog
Synthesis Tool : VIVADO
MIG Output Options:
Module Name : mig_7series_0
No of Controllers : 1
Selected Compatible Device(s) : --
FPGA Options:
System Clock Type : No Buffer
Reference Clock Type : No Buffer
Debug Port : OFF
Internal Vref : disabled
IO Power Reduction : ON
XADC instantiation in MIG : Disabled
Extended FPGA Options:
DCI for DQ,DQS/DQS#,DM : enabled
Internal Termination (HR Banks) : 40 Ohms
/*******************************************************/
/* Controller 0 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Interface : NATIVE
Design Clock Frequency : 2500 ps ( 0.00 MHz)
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 2500 ps
CLKFBOUT_MULT (PLL) : 2
DIVCLK_DIVIDE (PLL) : 1
VCC_AUX IO : 1.8V
Memory Type : Components
Memory Part : MT41J128M16XX-125
Equivalent Part(s) : MT41J128M16HA-125
Data Width : 16
ECC : Disabled
Data Mask : enabled
ORDERING : Normal
AXI Parameters :
Data Width : 128
Arbitration Scheme : RD_PRI_REG
Narrow Burst Support : 0
ID Width : 4
Memory Options:
Burst Length (MR0[1:0]) : 8 - Fixed
Read Burst Type (MR0[3]) : Sequential
CAS Latency (MR0[6:4]) : 6
Output Drive Strength (MR1[5,1]) : RZQ/7
Controller CS option : Disable
Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/6
Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
Memory Address Mapping : BANK_ROW_COLUMN
Bank Selections:
System_Control:
SignalName: sys_rst
PadLocation: No connect Bank: Select Bank
SignalName: init_calib_complete
PadLocation: No connect Bank: Select Bank
SignalName: tg_compare_error
PadLocation: No connect Bank: Select Bank