Subversion Repositories usb_nand_reader

_init_nand_data_line:
;NandDataLine.c,15 ::           void init_nand_data_line()
;NandDataLine.c,17 ::           TRISE = 0;
SW      R0, Offset(TRISE+0)(GP)
;NandDataLine.c,18 ::           TRISF = 0;
SW      R0, Offset(TRISF+0)(GP)
;NandDataLine.c,19 ::           TRISG = 0;
SW      R0, Offset(TRISG+0)(GP)
;NandDataLine.c,21 ::           LATE = 0;
SW      R0, Offset(LATE+0)(GP)
;NandDataLine.c,22 ::           LATF = 0;
SW      R0, Offset(LATF+0)(GP)
;NandDataLine.c,23 ::           LATG = 0;
SW      R0, Offset(LATG+0)(GP)
;NandDataLine.c,25 ::           nand_b0 = 0;
LUI     R2, BitMask(LATE2_bit+0)
ORI     R2, R2, BitMask(LATE2_bit+0)
_SX     
;NandDataLine.c,26 ::           nand_b1 = 0;
LUI     R2, BitMask(LATE3_bit+0)
ORI     R2, R2, BitMask(LATE3_bit+0)
_SX     
;NandDataLine.c,27 ::           nand_b2 = 0;
LUI     R2, BitMask(LATG7_bit+0)
ORI     R2, R2, BitMask(LATG7_bit+0)
_SX     
;NandDataLine.c,28 ::           nand_b3 = 0;
LUI     R2, BitMask(LATG8_bit+0)
ORI     R2, R2, BitMask(LATG8_bit+0)
_SX     
;NandDataLine.c,29 ::           nand_b4 = 0;
LUI     R2, BitMask(LATF5_bit+0)
ORI     R2, R2, BitMask(LATF5_bit+0)
_SX     
;NandDataLine.c,30 ::           nand_b5 = 0;
LUI     R2, BitMask(LATF4_bit+0)
ORI     R2, R2, BitMask(LATF4_bit+0)
_SX     
;NandDataLine.c,31 ::           nand_b6 = 0;
LUI     R2, BitMask(LATE4_bit+0)
ORI     R2, R2, BitMask(LATE4_bit+0)
_SX     
;NandDataLine.c,32 ::           nand_b7 = 0;
LUI     R2, BitMask(LATE5_bit+0)
ORI     R2, R2, BitMask(LATE5_bit+0)
_SX     
;NandDataLine.c,33 ::           }
L_end_init_nand_data_line:
JR      RA
NOP     
; end of _init_nand_data_line
_data_line_write_byte:
;NandDataLine.c,38 ::           void data_line_write_byte(unsigned char b)
;NandDataLine.c,40 ::           if(data_line_last_op != NAND_LAST_OP_WRITE)
LH      R3, Offset(_data_line_last_op+0)(GP)
ORI     R2, R0, 1
BNE     R3, R2, L__data_line_write_byte5
NOP     
J       L_data_line_write_byte0
NOP     
L__data_line_write_byte5:
;NandDataLine.c,42 ::           TRISE2_bit = 0; TRISE3_bit = 0; TRISE4_bit = 0; TRISE5_bit = 0;
LUI     R2, BitMask(TRISE2_bit+0)
ORI     R2, R2, BitMask(TRISE2_bit+0)
_SX     
LUI     R2, BitMask(TRISE3_bit+0)
ORI     R2, R2, BitMask(TRISE3_bit+0)
_SX     
LUI     R2, BitMask(TRISE4_bit+0)
ORI     R2, R2, BitMask(TRISE4_bit+0)
_SX     
LUI     R2, BitMask(TRISE5_bit+0)
ORI     R2, R2, BitMask(TRISE5_bit+0)
_SX     
;NandDataLine.c,43 ::           TRISF4_bit = 0; TRISF5_bit = 0;
LUI     R2, BitMask(TRISF4_bit+0)
ORI     R2, R2, BitMask(TRISF4_bit+0)
_SX     
LUI     R2, BitMask(TRISF5_bit+0)
ORI     R2, R2, BitMask(TRISF5_bit+0)
_SX     
;NandDataLine.c,44 ::           TRISG7_bit = 0; TRISG8_bit = 0;
LUI     R2, BitMask(TRISG7_bit+0)
ORI     R2, R2, BitMask(TRISG7_bit+0)
_SX     
LUI     R2, BitMask(TRISG8_bit+0)
ORI     R2, R2, BitMask(TRISG8_bit+0)
_SX     
;NandDataLine.c,45 ::           data_line_last_op = NAND_LAST_OP_WRITE;
ORI     R2, R0, 1
SH      R2, Offset(_data_line_last_op+0)(GP)
;NandDataLine.c,46 ::           }
L_data_line_write_byte0:
;NandDataLine.c,47 ::           nand_b0 = (b) & 1;
ANDI    R3, R25, 1
_LX     
INS     R2, R3, BitPos(LATE2_bit+0), 1
_SX     
;NandDataLine.c,48 ::           nand_b1 = (b >> 1) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 1
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATE3_bit+0), 1
_SX     
;NandDataLine.c,49 ::           nand_b2 = (b >> 2) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 2
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATG7_bit+0), 1
_SX     
;NandDataLine.c,50 ::           nand_b3 = (b >> 3) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 3
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATG8_bit+0), 1
_SX     
;NandDataLine.c,51 ::           nand_b4 = (b >> 4) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 4
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATF5_bit+0), 1
_SX     
;NandDataLine.c,52 ::           nand_b5 = (b >> 5) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 5
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATF4_bit+0), 1
_SX     
;NandDataLine.c,53 ::           nand_b6 = (b >> 6) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 6
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATE4_bit+0), 1
_SX     
;NandDataLine.c,54 ::           nand_b7 = (b >> 7) & 1;
ANDI    R2, R25, 255
SRL     R2, R2, 7
ANDI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATE5_bit+0), 1
_SX     
;NandDataLine.c,55 ::           asm NOP;
NOP     
;NandDataLine.c,56 ::           asm NOP;
NOP     
;NandDataLine.c,57 ::           asm NOP;
NOP     
;NandDataLine.c,58 ::           }
L_end_data_line_write_byte:
JR      RA
NOP     
; end of _data_line_write_byte
_data_line_read_byte:
;NandDataLine.c,61 ::           unsigned char data_line_read_byte()
;NandDataLine.c,63 ::           unsigned char d = 0;
; d start address is: 16 (R4)
MOVZ    R4, R0, R0
;NandDataLine.c,64 ::           if(data_line_last_op != NAND_LAST_OP_READ)
LH      R2, Offset(_data_line_last_op+0)(GP)
BNE     R2, R0, L__data_line_read_byte8
NOP     
J       L_data_line_read_byte1
NOP     
L__data_line_read_byte8:
;NandDataLine.c,66 ::           TRISE2_bit = 1; TRISE3_bit = 1; TRISE4_bit = 1; TRISE5_bit = 1;
LUI     R2, BitMask(TRISE2_bit+0)
ORI     R2, R2, BitMask(TRISE2_bit+0)
_SX     
LUI     R2, BitMask(TRISE3_bit+0)
ORI     R2, R2, BitMask(TRISE3_bit+0)
_SX     
LUI     R2, BitMask(TRISE4_bit+0)
ORI     R2, R2, BitMask(TRISE4_bit+0)
_SX     
LUI     R2, BitMask(TRISE5_bit+0)
ORI     R2, R2, BitMask(TRISE5_bit+0)
_SX     
;NandDataLine.c,67 ::           TRISF4_bit = 1; TRISF5_bit = 1;
LUI     R2, BitMask(TRISF4_bit+0)
ORI     R2, R2, BitMask(TRISF4_bit+0)
_SX     
LUI     R2, BitMask(TRISF5_bit+0)
ORI     R2, R2, BitMask(TRISF5_bit+0)
_SX     
;NandDataLine.c,68 ::           TRISG7_bit = 1; TRISG8_bit = 1;
LUI     R2, BitMask(TRISG7_bit+0)
ORI     R2, R2, BitMask(TRISG7_bit+0)
_SX     
LUI     R2, BitMask(TRISG8_bit+0)
ORI     R2, R2, BitMask(TRISG8_bit+0)
_SX     
;NandDataLine.c,69 ::           data_line_last_op = NAND_LAST_OP_READ;
SH      R0, Offset(_data_line_last_op+0)(GP)
;NandDataLine.c,70 ::           }
L_data_line_read_byte1:
;NandDataLine.c,71 ::           d |= (unsigned char)PORTE.B2;//nand_b0;
LBU     R2, Offset(PORTE+0)(GP)
EXT     R2, R2, 2, 1
OR      R3, R4, R2
; d end address is: 16 (R4)
;NandDataLine.c,72 ::           d |= ((unsigned char)PORTE.B3 << 1);//nand_b1 << 1);
LBU     R2, Offset(PORTE+0)(GP)
EXT     R2, R2, 3, 1
ANDI    R2, R2, 255
SLL     R2, R2, 1
OR      R3, R3, R2
;NandDataLine.c,73 ::           d |= ((unsigned char)PORTG.B7 << 2);//nand_b2 << 2);
LBU     R2, Offset(PORTG+0)(GP)
EXT     R2, R2, 7, 1
ANDI    R2, R2, 255
SLL     R2, R2, 2
OR      R3, R3, R2
;NandDataLine.c,74 ::           d |= ((unsigned char)PORTG.B8 << 3);//nand_b3 << 3);
LBU     R2, Offset(PORTG+1)(GP)
EXT     R2, R2, 0, 1
ANDI    R2, R2, 255
SLL     R2, R2, 3
OR      R3, R3, R2
;NandDataLine.c,75 ::           d |= ((unsigned char)PORTF.B5 << 4);//nand_b4 << 4);
LBU     R2, Offset(PORTF+0)(GP)
EXT     R2, R2, 5, 1
ANDI    R2, R2, 255
SLL     R2, R2, 4
OR      R3, R3, R2
;NandDataLine.c,76 ::           d |= ((unsigned char)PORTF.B4 << 5);//nand_b5 << 5);
LBU     R2, Offset(PORTF+0)(GP)
EXT     R2, R2, 4, 1
ANDI    R2, R2, 255
SLL     R2, R2, 5
OR      R3, R3, R2
;NandDataLine.c,77 ::           d |= ((unsigned char)PORTE.B4 << 6);//nand_b6 << 6);
LBU     R2, Offset(PORTE+0)(GP)
EXT     R2, R2, 4, 1
ANDI    R2, R2, 255
SLL     R2, R2, 6
OR      R3, R3, R2
;NandDataLine.c,78 ::           d |= ((unsigned char)PORTE.B5 << 7);//nand_b7 << 7);
LBU     R2, Offset(PORTE+0)(GP)
EXT     R2, R2, 5, 1
ANDI    R2, R2, 255
SLL     R2, R2, 7
OR      R2, R3, R2
;NandDataLine.c,79 ::           return d;
;NandDataLine.c,80 ::           }
L_end_data_line_read_byte:
JR      RA
NOP     
; end of _data_line_read_byte