Subversion Repositories usb_nand_reader

_main:
;main.c,48 ::           void main(void)
ADDIU   SP, SP, -4
;main.c,50 ::           char   hasId = 0;
MOVZ    R30, R0, R0
SB      R30, 2(SP)
MOVZ    R30, R0, R0
SB      R30, 3(SP)
;main.c,51 ::           char   hasOnfiParameterPage = 0;
;main.c,53 ::           AD1PCFG = 0xFFFF;
ORI     R2, R0, 65535
SW      R2, Offset(AD1PCFG+0)(GP)
;main.c,54 ::           TRISG6_bit = 0;
LUI     R2, BitMask(TRISG6_bit+0)
ORI     R2, R2, BitMask(TRISG6_bit+0)
_SX     
;main.c,55 ::           LATG6_bit = 0;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
;main.c,56 ::           TRISD6_bit = 0;
LUI     R2, BitMask(TRISD6_bit+0)
ORI     R2, R2, BitMask(TRISD6_bit+0)
_SX     
;main.c,57 ::           LATD6_bit = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,59 ::           init_nand_data_line();
JAL     _init_nand_data_line+0
NOP     
;main.c,60 ::           init_nand_control_line();
JAL     _init_nand_control_line+0
NOP     
;main.c,62 ::           MM_Init();
JAL     _MM_Init+0
NOP     
;main.c,64 ::           HID_Enable(&readbuff,&writebuff);
LUI     R26, hi_addr(_writebuff+0)
ORI     R26, R26, lo_addr(_writebuff+0)
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _HID_Enable+0
NOP     
;main.c,65 ::           if(U1CON.JSTATE == 0)
LBU     R2, Offset(U1CON+0)(GP)
EXT     R2, R2, 7, 1
BEQ     R2, R0, L__main61
NOP     
J       L_main0
NOP     
L__main61:
;main.c,67 ::           LATG6_bit = 1;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
;main.c,68 ::           Delay_ms(1000);
LUI     R24, 406
ORI     R24, R24, 59050
L_main1:
ADDIU   R24, R24, -1
BNE     R24, R0, L_main1
NOP     
;main.c,69 ::           LATG6_bit = 0;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
;main.c,70 ::           }
J       L_main3
NOP     
L_main0:
;main.c,73 ::           LATD6_bit = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,74 ::           Delay_ms(1000);
LUI     R24, 406
ORI     R24, R24, 59050
L_main4:
ADDIU   R24, R24, -1
BNE     R24, R0, L_main4
NOP     
;main.c,75 ::           LATD6_bit = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,76 ::           }
L_main3:
;main.c,79 ::           while(1)
L_main6:
;main.c,81 ::           USB_Polling_Proc();
JAL     _USB_Polling_Proc+0
NOP     
;main.c,83 ::           kk = HID_Read();
JAL     _HID_Read+0
NOP     
SB      R2, Offset(_kk+0)(GP)
;main.c,84 ::           if(kk != 0)
ANDI    R2, R2, 255
BNE     R2, R0, L__main63
NOP     
J       L_main8
NOP     
L__main63:
;main.c,86 ::           switch(readbuff[0])
J       L_main9
NOP     
;main.c,88 ::           case NAND_CHIP_ENABLE:
L_main11:
;main.c,89 ::           cmd_chip_enable(readbuff);
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_enable+0
NOP     
;main.c,90 ::           CE_ON = 1;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
;main.c,91 ::           break;
J       L_main10
NOP     
;main.c,93 ::           case NAND_CHIP_DISABLE:
L_main12:
;main.c,94 ::           cmd_chip_disable();
JAL     _cmd_chip_disable+0
NOP     
;main.c,95 ::           CE_ON = 0;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
;main.c,96 ::           break;
J       L_main10
NOP     
;main.c,98 ::           case NAND_CHIP_RESET:
L_main13:
;main.c,99 ::           DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,100 ::          cmd_chip_reset();
JAL     _cmd_chip_reset+0
NOP     
;main.c,101 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,102 ::          break;
J       L_main10
NOP     
;main.c,104 ::          case NAND_CHIP_READ_ID:
L_main14:
;main.c,105 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,106 ::          cmd_chip_read_id(writebuff, 0);
MOVZ    R26, R0, R0
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _cmd_chip_read_id+0
NOP     
;main.c,107 ::          nandId[0] = writebuff[0];
LBU     R2, Offset(_writebuff+0)(GP)
SB      R2, Offset(_nandId+0)(GP)
;main.c,108 ::          nandId[1] = writebuff[1];
LBU     R2, Offset(_writebuff+1)(GP)
SB      R2, Offset(_nandId+1)(GP)
;main.c,109 ::          nandId[2] = writebuff[2];
LBU     R2, Offset(_writebuff+2)(GP)
SB      R2, Offset(_nandId+2)(GP)
;main.c,110 ::          nandId[3] = writebuff[3];
LBU     R2, Offset(_writebuff+3)(GP)
SB      R2, Offset(_nandId+3)(GP)
;main.c,111 ::          nandId[4] = writebuff[4];
LBU     R2, Offset(_writebuff+4)(GP)
SB      R2, Offset(_nandId+4)(GP)
;main.c,112 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,113 ::          hasId = 1;
ORI     R2, R0, 1
SB      R2, 2(SP)
;main.c,114 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,115 ::          break;
J       L_main10
NOP     
;main.c,117 ::          case NAND_CHIP_READ_ID_ONFI:
L_main15:
;main.c,118 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,119 ::          cmd_chip_read_id(writebuff, 0x20);
ORI     R26, R0, 32
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _cmd_chip_read_id+0
NOP     
;main.c,120 ::          if('O' == writebuff[0] && 'N' == writebuff[1] && 'F' == writebuff[2] && 'I' == writebuff[3])
LBU     R3, Offset(_writebuff+0)(GP)
ORI     R2, R0, 79
BEQ     R3, R2, L__main64
NOP     
J       L__main55
NOP     
L__main64:
LBU     R3, Offset(_writebuff+1)(GP)
ORI     R2, R0, 78
BEQ     R3, R2, L__main65
NOP     
J       L__main54
NOP     
L__main65:
LBU     R3, Offset(_writebuff+2)(GP)
ORI     R2, R0, 70
BEQ     R3, R2, L__main66
NOP     
J       L__main53
NOP     
L__main66:
LBU     R3, Offset(_writebuff+3)(GP)
ORI     R2, R0, 73
BEQ     R3, R2, L__main67
NOP     
J       L__main52
NOP     
L__main67:
L__main51:
;main.c,122 ::          isOnfi = 1;
ORI     R2, R0, 1
SB      R2, Offset(_isOnfi+0)(GP)
;main.c,123 ::          onfiParamPage = Malloc(0x100);
ORI     R25, R0, 256
JAL     _Malloc+0
NOP     
SW      R2, Offset(_onfiParamPage+0)(GP)
;main.c,124 ::          if(0 == onfiParamPage)
BEQ     R2, R0, L__main68
NOP     
J       L_main19
NOP     
L__main68:
;main.c,125 ::          isOnfi = 0;
SB      R0, Offset(_isOnfi+0)(GP)
L_main19:
;main.c,120 ::          if('O' == writebuff[0] && 'N' == writebuff[1] && 'F' == writebuff[2] && 'I' == writebuff[3])
L__main55:
L__main54:
L__main53:
L__main52:
;main.c,127 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,128 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,129 ::          break;
J       L_main10
NOP     
;main.c,131 ::          case NAND_CHIP_READ_PARAM_PAGE:
L_main20:
;main.c,132 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,133 ::          if(0 != onfiParamPage)
LW      R2, Offset(_onfiParamPage+0)(GP)
BNE     R2, R0, L__main70
NOP     
J       L_main21
NOP     
L__main70:
;main.c,136 ::          cmd_chip_read_param_page(onfiParamPage);
LW      R25, Offset(_onfiParamPage+0)(GP)
JAL     _cmd_chip_read_param_page+0
NOP     
;main.c,137 ::          for(i = 0; i < 4; i++)
; i start address is: 20 (R5)
MOVZ    R5, R0, R0
; i end address is: 20 (R5)
L_main22:
; i start address is: 20 (R5)
SEH     R2, R5
SLTI    R2, R2, 4
BNE     R2, R0, L__main71
NOP     
J       L_main23
NOP     
L__main71:
;main.c,139 ::          for(j = 0; j < 64; j++)
; j start address is: 24 (R6)
MOVZ    R6, R0, R0
; j end address is: 24 (R6)
; i end address is: 20 (R5)
L_main25:
; j start address is: 24 (R6)
; i start address is: 20 (R5)
SEH     R2, R6
SLTI    R2, R2, 64
BNE     R2, R0, L__main72
NOP     
J       L_main26
NOP     
L__main72:
;main.c,141 ::          writebuff[j] = onfiParamPage[i * 64 + j];
SEH     R3, R6
LUI     R2, hi_addr(_writebuff+0)
ORI     R2, R2, lo_addr(_writebuff+0)
ADDU    R4, R2, R3
SEH     R2, R5
SLL     R2, R2, 6
ADDU    R2, R2, R6
SEH     R3, R2
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDU    R2, R2, R3
LBU     R2, 0(R2)
SB      R2, 0(R4)
;main.c,139 ::          for(j = 0; j < 64; j++)
ADDIU   R2, R6, 1
SEH     R6, R2
;main.c,142 ::          }
; j end address is: 24 (R6)
J       L_main25
NOP     
L_main26:
;main.c,143 ::          HID_Write(&writebuff, 64);
SH      R5, 0(SP)
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
LH      R5, 0(SP)
;main.c,137 ::          for(i = 0; i < 4; i++)
ADDIU   R2, R5, 1
SEH     R5, R2
;main.c,144 ::          }
; i end address is: 20 (R5)
J       L_main22
NOP     
L_main23:
;main.c,145 ::          hasOnfiParameterPage = 1;
ORI     R2, R0, 1
SB      R2, 3(SP)
;main.c,146 ::          busWidth = 8 << (onfiParamPage[6] & 1);
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 6
LBU     R2, 0(R2)
ANDI    R2, R2, 1
ANDI    R3, R2, 255
ORI     R2, R0, 8
SLLV    R2, R2, R3
SH      R2, Offset(_busWidth+0)(GP)
;main.c,147 ::          }
J       L_main28
NOP     
L_main21:
;main.c,150 ::          writebuff[0] = 0;
SB      R0, Offset(_writebuff+0)(GP)
;main.c,151 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,152 ::          }
L_main28:
;main.c,153 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,154 ::          break;
J       L_main10
NOP     
;main.c,156 ::          case NAND_CHIP_READ_PAGE:
L_main29:
;main.c,158 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
LBU     R2, 2(SP)
BEQ     R2, R0, L__main73
NOP     
J       L__main57
NOP     
L__main73:
LBU     R2, 3(SP)
BEQ     R2, R0, L__main74
NOP     
J       L__main56
NOP     
L__main74:
L__main50:
;main.c,160 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,161 ::          break;
J       L_main10
NOP     
;main.c,158 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
L__main57:
L__main56:
;main.c,164 ::          if(hasOnfiParameterPage)
LBU     R2, 3(SP)
BNE     R2, R0, L__main76
NOP     
J       L_main33
NOP     
L__main76:
;main.c,166 ::          pageSize = *(unsigned int*)(onfiParamPage + 80) + *(unsigned short*)(onfiParamPage + 84);
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 80
LHU     R3, 0(R2)
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 84
LBU     R2, 0(R2)
ANDI    R2, R2, 255
ADDU    R2, R3, R2
SH      R2, Offset(_pageSize+0)(GP)
;main.c,167 ::          addressCycles = (*(onfiParamPage + 101) & 0x0f) + (*(onfiParamPage + 101) >> 4);
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 101
LBU     R2, 0(R2)
ANDI    R4, R2, 15
ANDI    R2, R2, 255
SRL     R2, R2, 4
ANDI    R3, R2, 255
ANDI    R2, R4, 255
ADDU    R2, R2, R3
SH      R2, Offset(_addressCycles+0)(GP)
;main.c,168 ::          }
L_main33:
;main.c,169 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,170 ::          cmd_chip_read_page(readbuff, /*pageBuffer*/ writebuff, pageSize, addressCycles);
LH      R28, Offset(_addressCycles+0)(GP)
LH      R27, Offset(_pageSize+0)(GP)
LUI     R26, hi_addr(_writebuff+0)
ORI     R26, R26, lo_addr(_writebuff+0)
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_read_page+0
NOP     
;main.c,171 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,172 ::          break;
J       L_main10
NOP     
;main.c,174 ::          case NAND_SET_CONFIG_DATA:
L_main34:
;main.c,175 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,176 ::          pageSize = *(int*)(readbuff + 1);
LWR     R2, Offset(_readbuff+1)(GP)
LWL     R2, Offset(_readbuff+4)(GP)
SH      R2, Offset(_pageSize+0)(GP)
;main.c,177 ::          addressCycles = *(readbuff + 5);
LBU     R2, Offset(_readbuff+5)(GP)
SH      R2, Offset(_addressCycles+0)(GP)
;main.c,178 ::          busWidth = *(readbuff + 6);
LBU     R2, Offset(_readbuff+6)(GP)
SH      R2, Offset(_busWidth+0)(GP)
;main.c,179 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,180 ::          break;
J       L_main10
NOP     
;main.c,182 ::          case NAND_CHIP_READ_CACHE_SEQ:
L_main35:
;main.c,184 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
LBU     R2, 2(SP)
BEQ     R2, R0, L__main77
NOP     
J       L__main59
NOP     
L__main77:
LBU     R2, 3(SP)
BEQ     R2, R0, L__main78
NOP     
J       L__main58
NOP     
L__main78:
L__main49:
;main.c,186 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,187 ::          break;
J       L_main10
NOP     
;main.c,184 ::          if(0 == hasId && 0 == hasOnfiParameterPage)
L__main59:
L__main58:
;main.c,190 ::          if(hasOnfiParameterPage)
LBU     R2, 3(SP)
BNE     R2, R0, L__main80
NOP     
J       L_main39
NOP     
L__main80:
;main.c,192 ::          pageSize = *(unsigned int*)(onfiParamPage + 80) + *(unsigned short*)(onfiParamPage + 84);
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 80
LHU     R3, 0(R2)
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 84
LBU     R2, 0(R2)
ANDI    R2, R2, 255
ADDU    R2, R3, R2
SH      R2, Offset(_pageSize+0)(GP)
;main.c,193 ::          addressCycles = (*(onfiParamPage + 101) & 0x0f) + (*(onfiParamPage + 101) >> 4);
LW      R2, Offset(_onfiParamPage+0)(GP)
ADDIU   R2, R2, 101
LBU     R2, 0(R2)
ANDI    R4, R2, 15
ANDI    R2, R2, 255
SRL     R2, R2, 4
ANDI    R3, R2, 255
ANDI    R2, R4, 255
ADDU    R2, R2, R3
SH      R2, Offset(_addressCycles+0)(GP)
;main.c,194 ::          }
L_main39:
;main.c,195 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,196 ::          if(0 != pageSize)
LH      R2, Offset(_pageSize+0)(GP)
BNE     R2, R0, L__main82
NOP     
J       L_main40
NOP     
L__main82:
;main.c,198 ::          USB_Polling_Proc();
JAL     _USB_Polling_Proc+0
NOP     
;main.c,199 ::          cmd_chip_read_page_cache_sequential(readbuff, /*pageBuffer*/ writebuff, pageSize, addressCycles);
LH      R28, Offset(_addressCycles+0)(GP)
LH      R27, Offset(_pageSize+0)(GP)
LUI     R26, hi_addr(_writebuff+0)
ORI     R26, R26, lo_addr(_writebuff+0)
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_read_page_cache_sequential+0
NOP     
;main.c,200 ::          }
L_main40:
;main.c,201 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,202 ::          break;
J       L_main10
NOP     
;main.c,204 ::          case NAND_CHIP_READ_STATUS:
L_main41:
;main.c,205 ::          writebuff[0] = cmd_chip_read_status();
JAL     _cmd_chip_read_status+0
NOP     
SB      R2, Offset(_writebuff+0)(GP)
;main.c,206 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,207 ::          break;
J       L_main10
NOP     
;main.c,209 ::          case NAND_CHIP_READ_UNIQUE_ID:
L_main42:
;main.c,210 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,211 ::          cmd_chip_read_unique_id(writebuff);
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _cmd_chip_read_unique_id+0
NOP     
;main.c,212 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,213 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,214 ::          break;
J       L_main10
NOP     
;main.c,216 ::          case NAND_CHIP_BLOCK_ERASE:
L_main43:
;main.c,217 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,218 ::          cmd_chip_block_erase(readbuff);
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_block_erase+0
NOP     
;main.c,219 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,220 ::          break;
J       L_main10
NOP     
;main.c,222 ::          case NAND_CHIP_TOGGLE_WP:
L_main44:
;main.c,223 ::          nand_toggle_wp();
JAL     _nand_toggle_wp+0
NOP     
;main.c,224 ::          break;
J       L_main10
NOP     
;main.c,226 ::          case NAND_CHIP_PAGE_PROGRAM:
L_main45:
;main.c,227 ::          DAT_ON = 1;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,228 ::          if(0 != pageSize)
LH      R2, Offset(_pageSize+0)(GP)
BNE     R2, R0, L__main84
NOP     
J       L_main46
NOP     
L__main84:
;main.c,229 ::          cmd_chip_page_program(readbuff, addressCycles, pageSize);
LH      R27, Offset(_pageSize+0)(GP)
LH      R26, Offset(_addressCycles+0)(GP)
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_page_program+0
NOP     
L_main46:
;main.c,230 ::          DAT_ON = 0;
LUI     R2, BitMask(LATD6_bit+0)
ORI     R2, R2, BitMask(LATD6_bit+0)
_SX     
;main.c,231 ::          break;
J       L_main10
NOP     
;main.c,233 ::          case NAND_CHIP_READ_STATUS_ENHANCED:
L_main47:
;main.c,234 ::          writebuff[0] = cmd_chip_read_status_enhanced(readbuff, addressCycles);
LH      R26, Offset(_addressCycles+0)(GP)
LUI     R25, hi_addr(_readbuff+0)
ORI     R25, R25, lo_addr(_readbuff+0)
JAL     _cmd_chip_read_status_enhanced+0
NOP     
SB      R2, Offset(_writebuff+0)(GP)
;main.c,235 ::          HID_Write(&writebuff, 64);
ORI     R26, R0, 64
LUI     R25, hi_addr(_writebuff+0)
ORI     R25, R25, lo_addr(_writebuff+0)
JAL     _HID_Write+0
NOP     
;main.c,236 ::          break;
J       L_main10
NOP     
;main.c,238 ::          default:
L_main48:
;main.c,239 ::          break;
J       L_main10
NOP     
;main.c,240 ::          }
L_main9:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 1
BNE     R3, R2, L__main86
NOP     
J       L_main11
NOP     
L__main86:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 2
BNE     R3, R2, L__main88
NOP     
J       L_main12
NOP     
L__main88:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 3
BNE     R3, R2, L__main90
NOP     
J       L_main13
NOP     
L__main90:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 4
BNE     R3, R2, L__main92
NOP     
J       L_main14
NOP     
L__main92:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 5
BNE     R3, R2, L__main94
NOP     
J       L_main15
NOP     
L__main94:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 6
BNE     R3, R2, L__main96
NOP     
J       L_main20
NOP     
L__main96:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 7
BNE     R3, R2, L__main98
NOP     
J       L_main29
NOP     
L__main98:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 8
BNE     R3, R2, L__main100
NOP     
J       L_main34
NOP     
L__main100:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 9
BNE     R3, R2, L__main102
NOP     
J       L_main35
NOP     
L__main102:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 10
BNE     R3, R2, L__main104
NOP     
J       L_main41
NOP     
L__main104:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 11
BNE     R3, R2, L__main106
NOP     
J       L_main42
NOP     
L__main106:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 12
BNE     R3, R2, L__main108
NOP     
J       L_main43
NOP     
L__main108:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 13
BNE     R3, R2, L__main110
NOP     
J       L_main44
NOP     
L__main110:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 14
BNE     R3, R2, L__main112
NOP     
J       L_main45
NOP     
L__main112:
LBU     R3, Offset(_readbuff+0)(GP)
ORI     R2, R0, 15
BNE     R3, R2, L__main114
NOP     
J       L_main47
NOP     
L__main114:
J       L_main48
NOP     
L_main10:
;main.c,241 ::          }
L_main8:
;main.c,242 ::          }
J       L_main6
NOP     
;main.c,259 ::          }
L_end_main:
L__main_end_loop:
J       L__main_end_loop
NOP     
; end of _main