Subversion Repositories usbhostslave

VERSION=1.15
HEADER
FILE="usbTxWireArbiter.asf"
FID=4053e959
LANGUAGE=VERILOG
ENTITY="USBTxWireArbiter"
FRAMES=ON
FREEOID=128
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: usbTxWireArbiter.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
END
BUNDLES
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
END
INSTHEADER 1
PAGE 25400,0 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 5000,5000 10000,10000
END
OBJECTS
S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
I 20 6 0 Builtin Reset | 86247,136033
A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
I 59 0 3 Builtin InPort | 200032,246137 "" ""
L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
I 61 0 2 Builtin InPort | 199418,251681 "" ""
C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
                                      200193,83454 202194,93721 199799,97969 197405,102218\
                                      189371,107780 182843,108050 176316,108321 158239,103840\
                                      151634,101445 145030,99051 137656,94031 133485,91482
C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n  end\nend"
C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
                                      70311,70629 71874,86691 76817,93064 81761,99437\
                                      89642,107471 97173,106158 104705,104845 116882,95874\
                                      123371,91703
A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
I 95 0 2 Builtin Signal | 187475,230225 "" ""
I 111 0 2 Builtin OutPort | 153906,181456 "" ""
L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
I 109 0 2 Builtin InPort | 156447,157894 "" ""
L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
I 107 0 2 Builtin InPort | 156216,186076 "" ""
L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
I 105 0 2 Builtin OutPort | 154368,153274 "" ""
L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
I 103 0 2 Builtin OutPort | 142325,212440 "" ""
L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
I 101 0 130 Builtin OutPort | 142556,217291 "" ""
L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
I 99 0 2 Builtin OutPort | 142787,221911 "" ""
L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
I 127 0 2 Builtin OutPort | 141972,231298 "" ""
L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
I 125 0 2 Builtin InPort | 144051,235918 "" ""
L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
I 123 0 2 Builtin InPort | 155985,199705 "" ""
L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
I 121 0 2 Builtin InPort | 155985,195316 "" ""
L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
I 119 0 130 Builtin InPort | 155985,190696 "" ""
L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
I 117 0 2 Builtin InPort | 156447,171985 "" ""
L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
I 115 0 2 Builtin InPort | 156447,167596 "" ""
L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
I 113 0 130 Builtin InPort | 156447,162745 "" ""
L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
END