Subversion Repositories usbhostslave

VERSION=1.15
HEADER
FILE="slaveDirectcontrol.asf"
FID=406ac3b6
LANGUAGE=VERILOG
ENTITY="slaveDirectControl"
FRAMES=ON
FREEOID=180
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n"
END
BUNDLES
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
END
INSTHEADER 1
PAGE 12700,12700 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 5000,5000 10000,10000
END
INSTHEADER 78
PAGE 12700,12700 215900,279400
UPPERLEFT 0,0
GRID=OFF
GRIDSIZE 0,0 10000,10000
END
INSTHEADER 127
PAGE 12700,12700 215900,279400
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GRIDSIZE 0,0 10000,10000
END
OBJECTS
L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
I 13 6 0 Builtin Reset | 48900,215400
S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_SDC\n/0/"
L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "slvDrctCntl"
F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: slaveDirectControl"
C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
I 21 0 2 Builtin InPort | 57252,239123 "" ""
L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
I 18 0 2 Builtin InPort | 181500,257400 "" ""
L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
I 16 0 3 Builtin InPort | 181300,263800 "" ""
W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "SCTxPortWEn <= 1'b0;"
S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
                                           46421,89345 46021,97345 47471,100295 48921,103245\
                                           55748,105011 58848,106911
L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "SCTxPortGnt == 1'b1"
W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "SCTxPortRdy == 1'b1"
A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
                                       47285,153175 50048,167625 56316,171290 62585,174956\
                                       84856,175714 96012,175820
I 124 79 0 Builtin Entry | 109800,175900
I 122 79 0 Builtin Exit | 138103,36586
S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "SCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "SCTxPortRdy == 1'b1"
W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "SCTxPortGnt == 1'b1"
W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "SCTxPortWEn"
I 158 0 2 Builtin OutPort | 109163,245109 "" ""
L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "SCTxPortData[7:0]"
I 156 0 130 Builtin OutPort | 109440,251139 "" ""
L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "SCTxPortCntl[7:0]"
I 154 0 130 Builtin OutPort | 108837,257571 "" ""
W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
                                        171826,160150 159742,169266 150997,171704 142252,174142\
                                        120424,175336 108976,175654
I 151 128 0 Builtin Exit | 67380,61048
I 150 128 0 Builtin Entry | 67068,204814
A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "SCTxPortReq <= 1'b1;"
L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "SCTxPortReq <= 1'b1;"
A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "SCTxPortCntl <= 8'h00;\nSCTxPortData <= 8'h00;\nSCTxPortWEn <= 1'b0;   \nSCTxPortReq <= 1'b0;"
L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "SCTxPortReq"
I 164 0 2 Builtin OutPort | 160587,239893 "" ""
L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "SCTxPortGnt"
I 162 0 2 Builtin InPort | 162999,244717 "" ""
L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "SCTxPortRdy"
I 160 0 2 Builtin InPort | 111543,239893 "" ""
W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
I 179 0 130 Builtin InPort | 57352,247790 "" ""
END