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URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [usbDevice/] [syn/] [Actel/] [usbDeviceActelTop/] [usbDeviceActelTop.prj] - Rev 44

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KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\RTL"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "IGLOO"
KEY VendorTechnology_Die "IS6X6M2LP"
KEY VendorTechnology_Package "fg256"
KEY ProjectLocation "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "usbDeviceActelTop::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\constraint\usbDeviceActelTop.pdc,pdc"
STATE="utd"
TIME="1207237677"
SIZE="6506"
ENDFILE
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
STATE="ood"
TIME="1219427579"
SIZE="1078784"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
STATE="utd"
TIME="1219440016"
SIZE="1136640"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.pdb,pdb"
STATE="utd"
TIME="1219441261"
SIZE="16384"
ENDFILE
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
STATE="utd"
TIME="1219441266"
SIZE="293941"
ENDFILE
VALUE "<project>\hdl\checkLineState.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="6885"
ENDFILE
VALUE "<project>\hdl\dpMem_dc.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="3862"
ENDFILE
VALUE "<project>\hdl\endpMux.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="8260"
ENDFILE
VALUE "<project>\hdl\EP0.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="25833"
ENDFILE
VALUE "<project>\hdl\EP1Mouse.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="9454"
ENDFILE
VALUE "<project>\hdl\fifoMux.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="6575"
ENDFILE
VALUE "<project>\hdl\fifoRTL.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="6307"
ENDFILE
VALUE "<project>\hdl\hostSlaveMuxBI.v,hdl"
STATE="utd"
TIME="1219427436"
SIZE="4931"
ENDFILE
VALUE "<project>\hdl\lineControlUpdate.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="3451"
ENDFILE
VALUE "<project>\hdl\processRxBit.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="15071"
ENDFILE
VALUE "<project>\hdl\processRxByte.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="17214"
ENDFILE
VALUE "<project>\hdl\processTxByte.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="15227"
ENDFILE
VALUE "<project>\hdl\readUSBWireData.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="10944"
ENDFILE
VALUE "<project>\hdl\RxFifo.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5079"
ENDFILE
VALUE "<project>\hdl\RxFifoBI.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5600"
ENDFILE
VALUE "<project>\hdl\sctxportarbiter.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="7476"
ENDFILE
VALUE "<project>\hdl\siereceiver.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="9992"
ENDFILE
VALUE "<project>\hdl\SIETransmitter.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="24223"
ENDFILE
VALUE "<project>\hdl\slavecontroller.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="17626"
ENDFILE
VALUE "<project>\hdl\slaveDirectcontrol.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="7433"
ENDFILE
VALUE "<project>\hdl\slaveGetpacket.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="12832"
ENDFILE
VALUE "<project>\hdl\slaveRxStatusMonitor.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="3985"
ENDFILE
VALUE "<project>\hdl\slaveSendpacket.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="9072"
ENDFILE
VALUE "<project>\hdl\timescale.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="230"
ENDFILE
VALUE "<project>\hdl\TxFifo.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5002"
ENDFILE
VALUE "<project>\hdl\TxFifoBI.v,hdl"
STATE="utd"
TIME="1219427411"
SIZE="5596"
ENDFILE
VALUE "<project>\hdl\updateCRC16.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="4076"
ENDFILE
VALUE "<project>\hdl\updateCRC5.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="4274"
ENDFILE
VALUE "<project>\hdl\usbConstants_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="706"
ENDFILE
VALUE "<project>\hdl\usbDevice.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="6821"
ENDFILE
VALUE "<project>\hdl\usbDeviceActelTop.v,hdl"
STATE="utd"
TIME="1219440128"
SIZE="1329"
ENDFILE
VALUE "<project>\hdl\usbDevice_define.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="1297"
ENDFILE
VALUE "<project>\hdl\usbHostControl_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="2187"
ENDFILE
VALUE "<project>\hdl\usbHostSlaveReg_define.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="5597"
ENDFILE
VALUE "<project>\hdl\usbHostSlave_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="5297"
ENDFILE
VALUE "<project>\hdl\usbROM.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="12466"
ENDFILE
VALUE "<project>\hdl\usbSerialInterfaceEngine.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="11255"
ENDFILE
VALUE "<project>\hdl\usbSerialInterfaceEngine_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="3284"
ENDFILE
VALUE "<project>\hdl\usbSlave.v,hdl"
STATE="utd"
TIME="1219427483"
SIZE="15345"
ENDFILE
VALUE "<project>\hdl\usbSlaveControl.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="15326"
ENDFILE
VALUE "<project>\hdl\USBSlaveControlBI.v,hdl"
STATE="utd"
TIME="1219427470"
SIZE="24769"
ENDFILE
VALUE "<project>\hdl\usbSlaveControl_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="2718"
ENDFILE
VALUE "<project>\hdl\usbTxWireArbiter.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="7513"
ENDFILE
VALUE "<project>\hdl\wishboneArb.v,hdl"
STATE="utd"
TIME="1219425593"
SIZE="5708"
ENDFILE
VALUE "<project>\hdl\wishBoneBI.v,hdl"
STATE="utd"
TIME="1219427420"
SIZE="8684"
ENDFILE
VALUE "<project>\hdl\wishBoneBus_h.v,hdl"
STATE="utd"
TIME="1219427448"
SIZE="1041"
ENDFILE
VALUE "<project>\hdl\writeUSBWireData.v,hdl"
STATE="utd"
TIME="1219427458"
SIZE="8542"
ENDFILE
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
STATE="utd"
TIME="1219427525"
SIZE="3585871"
ENDFILE
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
STATE="utd"
TIME="1219439810"
SIZE="3661567"
ENDFILE
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219439810"
SIZE="376"
ENDFILE
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1219427525"
SIZE="376"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "usbDevice::work"
FILE "<project>\hdl\usbDevice.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
VALUE "<project>\designer\impl1\usbDevice.prb,prb"
VALUE "<project>\designer\impl1\usbDevice.stp,stp"
VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "usbDeviceActelTop::work"
FILE "<project>\hdl\usbDeviceActelTop.v,hdl"
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=coreconsole
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=C:\Libero\Synplify\Synplify_902A2\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=C:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "usbDevice::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDevice.adb,adb"
VALUE "<project>\designer\impl1\usbDevice.prb,prb"
VALUE "<project>\designer\impl1\usbDevice.stp,stp"
VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "usbDeviceActelTop::work"
LIST Impl1
LiberoState=Post_Layout
ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
ACTIVE_VIEW:0
ENDLIST

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