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[/] [usbhostslave/] [trunk/] [usbDevice/] [syn/] [xilinx/] [usbDeviceXilinxTop/] [pll_48MHz_xilinx.v] - Rev 40
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//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 9.2.03i // \ \ Application : xaw2verilog // / / Filename : pll_48MHz_xilinx.v // /___/ /\ Timestamp : 08/20/2008 15:22:39 // \ \ / \ // \___\/\___\ // //Command: xaw2verilog -intstyle F:/version_ctrl/usbhostslave/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw -st pll_48MHz_xilinx.v //Design Name: pll_48MHz_xilinx //Device: xc3s700a-5fg484 // // Module pll_48MHz_xilinx // Generated by Xilinx Architecture Wizard // Written for synthesis tool: XST `timescale 1ns / 1ps module pll_48MHz_xilinx(CLKIN_IN, CLKIN_IBUFG_OUT, CLK0_OUT, LOCKED_OUT); input CLKIN_IN; output CLKIN_IBUFG_OUT; output CLK0_OUT; output LOCKED_OUT; wire CLKFB_IN; wire CLKIN_IBUFG; wire CLK0_BUF; wire GND_BIT; assign GND_BIT = 0; assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; assign CLK0_OUT = CLKFB_IN; IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), .O(CLKIN_IBUFG)); BUFG CLK0_BUFG_INST (.I(CLK0_BUF), .O(CLKFB_IN)); DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN), .CLKIN(CLKIN_IBUFG), .DSSEN(GND_BIT), .PSCLK(GND_BIT), .PSEN(GND_BIT), .PSINCDEC(GND_BIT), .RST(GND_BIT), .CLKDV(), .CLKFX(), .CLKFX180(), .CLK0(CLK0_BUF), .CLK2X(), .CLK2X180(), .CLK90(), .CLK180(), .CLK270(), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); defparam DCM_SP_INST.CLK_FEEDBACK = "1X"; defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; defparam DCM_SP_INST.CLKFX_DIVIDE = 1; defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_SP_INST.CLKIN_PERIOD = 20.833; defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_SP_INST.FACTORY_JF = 16'hC080; defparam DCM_SP_INST.PHASE_SHIFT = 0; defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; endmodule