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--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="fibonacci.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=12 WIDTHAD_A=9 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END-- Copyright (C) 1991-2010 Altera Corporation-- Your use of Altera Corporation's design tools, logic functions-- and other software and tools, and its AMPP partner logic-- functions, and any output files from any of the foregoing-- (including device programming or simulation files), and any-- associated documentation or information are expressly subject-- to the terms and conditions of the Altera Program License-- Subscription Agreement, Altera MegaCore Function License-- Agreement, or other applicable license agreement, including,-- without limitation, that your use is for the sole purpose of-- programming logic devices manufactured by Altera and sold by-- Altera or its authorized distributors. Please refer to the-- applicable agreement for further details.FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);--synthesis_resources = ram_bits (AUTO) 6144OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";SUBDESIGN altsyncram_im61(address_a[8..0] : input;clock0 : input;data_a[11..0] : input;q_a[11..0] : output;wren_a : input;)VARIABLEram_block1a0 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 0,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a1 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 1,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a2 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 2,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a3 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 3,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a4 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 4,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a5 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 5,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a6 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 6,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a7 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 7,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a8 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 8,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a9 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 9,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a10 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 10,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");ram_block1a11 : stratixii_ram_blockWITH (CONNECTIVITY_CHECKING = "OFF",INIT_FILE = "fibonacci.mif",INIT_FILE_LAYOUT = "port_a",LOGICAL_RAM_NAME = "ALTSYNCRAM",OPERATION_MODE = "single_port",PORT_A_ADDRESS_WIDTH = 9,PORT_A_DATA_OUT_CLEAR = "none",PORT_A_DATA_OUT_CLOCK = "none",PORT_A_DATA_WIDTH = 1,PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",PORT_A_FIRST_ADDRESS = 0,PORT_A_FIRST_BIT_NUMBER = 11,PORT_A_LAST_ADDRESS = 511,PORT_A_LOGICAL_RAM_DEPTH = 512,PORT_A_LOGICAL_RAM_WIDTH = 12,RAM_BLOCK_TYPE = "AUTO");address_a_wire[8..0] : WIRE;BEGINram_block1a[11..0].clk0 = clock0;ram_block1a[11..0].portaaddr[] = ( address_a_wire[8..0]);ram_block1a[0].portadatain[] = ( data_a[0..0]);ram_block1a[1].portadatain[] = ( data_a[1..1]);ram_block1a[2].portadatain[] = ( data_a[2..2]);ram_block1a[3].portadatain[] = ( data_a[3..3]);ram_block1a[4].portadatain[] = ( data_a[4..4]);ram_block1a[5].portadatain[] = ( data_a[5..5]);ram_block1a[6].portadatain[] = ( data_a[6..6]);ram_block1a[7].portadatain[] = ( data_a[7..7]);ram_block1a[8].portadatain[] = ( data_a[8..8]);ram_block1a[9].portadatain[] = ( data_a[9..9]);ram_block1a[10].portadatain[] = ( data_a[10..10]);ram_block1a[11].portadatain[] = ( data_a[11..11]);ram_block1a[11..0].portawe = wren_a;address_a_wire[] = address_a[];q_a[] = ( ram_block1a[11..0].portadataout[0..0]);END;--VALID FILE