Subversion Repositories usimplez

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 11:45:48 2011 " "Info: Processing started: Wed Nov 09 11:45:48 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_cpu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_cpu-fsm " "Info: Found design unit 1: usimplez_cpu-fsm" {  } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 86 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_cpu " "Info: Found entity 1: usimplez_cpu" {  } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 52 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_ram-rtl " "Info: Found design unit 1: usimplez_ram-rtl" {  } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_ram.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_ram " "Info: Found entity 1: usimplez_ram" {  } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_ram.vhd" 54 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_top-str " "Info: Found design unit 1: usimplez_top-str" {  } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 69 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_top " "Info: Found entity 1: usimplez_top" {  } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "usimplez_top " "Info: Elaborating entity \"usimplez_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_cpu usimplez_cpu:cpu " "Info: Elaborating entity \"usimplez_cpu\" for hierarchy \"usimplez_cpu:cpu\"" {  } { { "usimplez_top.vhd" "cpu" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 123 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_ram usimplez_ram:ram " "Info: Elaborating entity \"usimplez_ram\" for hierarchy \"usimplez_ram:ram\"" {  } { { "usimplez_top.vhd" "ram" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 150 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "usimplez_ram:ram\|ram~22 " "Info: Inferred altsyncram megafunction from the following design logic: \"usimplez_ram:ram\|ram~22\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 12 " "Info: Parameter WIDTH_A set to 12" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Info: Parameter WIDTHAD_A set to 9" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Info: Parameter NUMWORDS_A set to 512" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE fibonacci.mif " "Info: Parameter INIT_FILE set to fibonacci.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1}  } { { "usimplez_ram.vhd" "ram~22" { Text "C:/Altera/qdesigns/usimplez00/usimplez_ram.vhd" 76 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"usimplez_ram:ram\|altsyncram:ram_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Instantiated megafunction \"usimplez_ram:ram\|altsyncram:ram_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Info: Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 12 " "Info: Parameter \"WIDTH_A\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Info: Parameter \"WIDTHAD_A\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Info: Parameter \"NUMWORDS_A\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Info: Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE fibonacci.mif " "Info: Parameter \"INIT_FILE\" = \"fibonacci.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_im61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_im61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_im61 " "Info: Found entity 1: altsyncram_im61" {  } { { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_im61.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "94 " "Info: Implemented 94 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 11:45:57 2011 " "Info: Processing ended: Wed Nov 09 11:45:57 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}