URL
https://opencores.org/ocsvn/usimplez/usimplez/trunk
Subversion Repositories usimplez
[/] [usimplez/] [trunk/] [QuartusII/] [db/] [prev_cmp_usimplez_top.tan.qmsg] - Rev 3
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 11:44:01 2011 " "Info: Processing started: Wed Nov 09 11:44:01 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez_top" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "we_o 0 " "Info: Pin \"we_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in0_o 0 " "Info: Pin \"in0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in1_o 0 " "Info: Pin \"in1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } {} 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op0_o 0 " "Info: Pin \"op0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op1_o 0 " "Info: Pin \"op1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i memory usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg register usimplez_cpu:cpu\|ac_reg_s\[11\] 134.37 MHz 7.442 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 134.37 MHz between source memory \"usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg\" and destination register \"usimplez_cpu:cpu\|ac_reg_s\[11\]\" (period= 7.442 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.628 ns + Longest memory register " "Info: + Longest memory to register delay is 3.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X32_Y15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.850 ns) 1.850 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a1 2 MEM M4K_X32_Y15 4 " "Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X32_Y15; Fanout = 4; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_regusimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 } "NODE_NAME" } } { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 56 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.436 ns) 3.030 ns usimplez_cpu:cpu\|Add2~7 3 COMB LCCOMB_X30_Y14_N2 2 " "Info: 3: + IC(0.744 ns) + CELL(0.436 ns) = 3.030 ns; Loc. = LCCOMB_X30_Y14_N2; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.065 ns usimplez_cpu:cpu\|Add2~11 4 COMB LCCOMB_X30_Y14_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.065 ns; Loc. = LCCOMB_X30_Y14_N4; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~11'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.100 ns usimplez_cpu:cpu\|Add2~15 5 COMB LCCOMB_X30_Y14_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.100 ns; Loc. = LCCOMB_X30_Y14_N6; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~15'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.135 ns usimplez_cpu:cpu\|Add2~19 6 COMB LCCOMB_X30_Y14_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.135 ns; Loc. = LCCOMB_X30_Y14_N8; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~19'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.170 ns usimplez_cpu:cpu\|Add2~23 7COMB LCCOMB_X30_Y14_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.170 ns; Loc. = LCCOMB_X30_Y14_N10; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.205 ns usimplez_cpu:cpu\|Add2~27 8 COMB LCCOMB_X30_Y14_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 3.205 ns; Loc. = LCCOMB_X30_Y14_N12; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~27'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 3.301 ns usimplez_cpu:cpu\|Add2~31 9 COMB LCCOMB_X30_Y14_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 3.301 ns; Loc. = LCCOMB_X30_Y14_N14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~31'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.336 ns usimplez_cpu:cpu\|Add2~35 10 COMB LCCOMB_X30_Y14_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.336 ns; Loc. = LCCOMB_X30_Y14_N16; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~35'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.371 ns usimplez_cpu:cpu\|Add2~39 11 COMB LCCOMB_X30_Y14_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 3.371 ns; Loc. = LCCOMB_X30_Y14_N18; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~39'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.406 ns usimplez_cpu:cpu\|Add2~43 12 COMB LCCOMB_X30_Y14_N20 1 " "Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 3.406 ns; Loc. = LCCOMB_X30_Y14_N20; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~43'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 3.531 ns usimplez_cpu:cpu\|Add2~46 13 COMB LCCOMB_X30_Y14_N22 1 " "Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 3.531 ns; Loc. = LCCOMB_X30_Y14_N22; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 204 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.097 ns) 3.628 ns usimplez_cpu:cpu\|ac_reg_s\[11\] 14 REG LCFF_X30_Y14_N23 3 " "Info: 14: + IC(0.000 ns) + CELL(0.097 ns) = 3.628 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|ac_reg_s\[11\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.097 ns" { usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.884 ns ( 79.49 % ) " "Info: Total cell delay = 2.884 ns ( 79.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.744 ns ( 20.51 % ) " "Info: Total interconnect delay = 0.744 ns ( 20.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.628 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.628 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 {} usimplez_cpu:cpu|Add2~7 {} usimplez_cpu:cpu|Add2~11 {} usimplez_cpu:cpu|Add2~15 {} usimplez_cpu:cpu|Add2~19 {} usimplez_cpu:cpu|Add2~23 {} usimplez_cpu:cpu|Add2~27 {} usimplez_cpu:cpu|Add2~31 {} usimplez_cpu:cpu|Add2~35 {} usimplez_cpu:cpu|Add2~39 {} usimplez_cpu:cpu|Add2~43 {} usimplez_cpu:cpu|Add2~46 {} usimplez_cpu:cpu|ac_reg_s[11] {} } { 0.000ns 0.000ns 0.744ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.850ns 0.436ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.035ns 0.035ns 0.125ns 0.097ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.133 ns - Smallest " "Info: - Smallest clock skew is 0.133 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.481 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { {"c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 2.481 ns usimplez_cpu:cpu\|ac_reg_s\[11\] 3 REG LCFF_X30_Y14_N23 3 " "Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|ac_reg_s\[11\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clk_i~clkctrl usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.33 % ) " "Info: Total cell delay = 1.472 ns ( 59.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 40.67 % ) " "Info: Total interconnect delay = 1.009 ns ( 40.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|ac_reg_s[11] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.348 ns - Longest memory " "Info: - Longest clock path from clock \"clk_i\" to source memory is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.481 ns) 2.348 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X32_Y15 3 " "Info: 3: + IC(0.670 ns) + CELL(0.481 ns) = 2.348 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_k961:auto_generated\|ram_block1a0~porta_we_reg'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.151 ns" { clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0"" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.335 ns ( 56.86 % ) " "Info: Total cell delay = 1.335 ns ( 56.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.013 ns ( 43.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|ac_reg_s[11] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" { } { { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 36 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "db/altsyncram_k961.tdf" "" { Text "C:/Altera/qdesigns/usimplez00/db/altsyncram_k961.tdf" 36 2 0 }} { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.628 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.628 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1 {} usimplez_cpu:cpu|Add2~7 {} usimplez_cpu:cpu|Add2~11 {} usimplez_cpu:cpu|Add2~15 {} usimplez_cpu:cpu|Add2~19 {} usimplez_cpu:cpu|Add2~23 {} usimplez_cpu:cpu|Add2~27 {} usimplez_cpu:cpu|Add2~31 {} usimplez_cpu:cpu|Add2~35 {} usimplez_cpu:cpu|Add2~39 {} usimplez_cpu:cpu|Add2~43 {} usimplez_cpu:cpu|Add2~46 {} usimplez_cpu:cpu|ac_reg_s[11] {} } { 0.000ns 0.000ns 0.744ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.850ns 0.436ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.035ns 0.035ns 0.125ns 0.097ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|ac_reg_s[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|ac_reg_s[11] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}{ "Info" "ITDB_TSU_RESULT" "usimplez_cpu:cpu\|cp_reg_s\[0\] rst_i clk_i 5.781 ns register " "Info: tsu for register \"usimplez_cpu:cpu\|cp_reg_s\[0\]\" (data pin = \"rst_i\", clock pin = \"clk_i\") is 5.781 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.152 ns + Longest pin register " "Info: + Longest pin to register delay is 8.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns rst_i 1 PIN PIN_W9 49 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.663 ns) + CELL(0.346 ns) 5.808 ns usimplez_cpu:cpu\|cp_reg_s\[6\]~1 2 COMB LCCOMB_X33_Y14_N30 9 " "Info: 2: +IC(4.663 ns) + CELL(0.346 ns) = 5.808 ns; Loc. = LCCOMB_X33_Y14_N30; Fanout = 9; COMB Node = 'usimplez_cpu:cpu\|cp_reg_s\[6\]~1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.009 ns" { rst_i usimplez_cpu:cpu|cp_reg_s[6]~1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.598 ns) + CELL(0.746 ns) 8.152 ns usimplez_cpu:cpu\|cp_reg_s\[0\] 3 REG LCFF_X19_Y9_N1 3 " "Info: 3: + IC(1.598 ns) + CELL(0.746 ns) = 8.152 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|cp_reg_s\[0\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.344 ns" { usimplez_cpu:cpu|cp_reg_s[6]~1 usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.891 ns ( 23.20 % ) " "Info: Total cell delay = 1.891 ns ( 23.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.261 ns ( 76.80 % ) " "Info: Total interconnect delay = 6.261 ns ( 76.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { rst_i usimplez_cpu:cpu|cp_reg_s[6]~1 usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|cp_reg_s[6]~1 {} usimplez_cpu:cpu|cp_reg_s[0] {} } { 0.000ns 0.000ns 4.663ns 1.598ns } { 0.000ns 0.799ns 0.346ns0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.461 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns usimplez_cpu:cpu\|cp_reg_s\[0\] 3 REG LCFF_X19_Y9_N1 3 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|cp_reg_s\[0\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" """1.264 ns" { clk_i~clkctrl usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|cp_reg_s[0]{} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.152 ns" { rst_i usimplez_cpu:cpu|cp_reg_s[6]~1 usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.152 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|cp_reg_s[6]~1 {} usimplez_cpu:cpu|cp_reg_s[0] {} } { 0.000ns 0.000ns 4.663ns 1.598ns } { 0.000ns 0.799ns 0.346ns 0.746ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|cp_reg_s[0] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|cp_reg_s[0] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i we_o usimplez_cpu:cpu\|we_o 6.520 ns register " "Info: tco from clock \"clk_i\" to destination pin \"we_o\" through register \"usimplez_cpu:cpu\|we_o\" is 6.520 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.467 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info:2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.652 ns) + CELL(0.618 ns) 2.467 ns usimplez_cpu:cpu\|we_o 3 REG LCFF_X18_Y14_N1 4 " "Info: 3: + IC(0.652 ns) + CELL(0.618 ns) = 2.467 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu\|we_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.270 ns" { clk_i~clkctrl usimplez_cpu:cpu|we_o } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.67 % ) " "Info: Total cell delay = 1.472 ns ( 59.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 40.33 % ) " "Info: Total interconnect delay = 0.995 ns ( 40.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.467 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|we_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.467 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|we_o {} } { 0.000ns 0.000ns 0.343ns 0.652ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 75 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.959 ns + Longest register pin " "Info: + Longest register to pin delay is 3.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_cpu:cpu\|we_o 1 REG LCFF_X18_Y14_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu\|we_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_cpu:cpu|we_o } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.977 ns) + CELL(1.982 ns) 3.959 ns we_o 2 PIN PIN_B8 0 " "Info: 2: + IC(1.977 ns) + CELL(1.982 ns) = 3.959 ns; Loc. = PIN_B8; Fanout = 0; PIN Node = 'we_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.959 ns" { usimplez_cpu:cpu|we_o we_o } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 61 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.982 ns ( 50.06 % ) " "Info: Total cell delay = 1.982 ns ( 50.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.977 ns ( 49.94 % ) " "Info: Total interconnect delay = 1.977 ns ( 49.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.959 ns" { usimplez_cpu:cpu|we_o we_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.959 ns" { usimplez_cpu:cpu|we_o {} we_o {} } { 0.000ns 1.977ns } { 0.000ns 1.982ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.467 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|we_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.467 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|we_o {} } { 0.000ns 0.000ns 0.343ns 0.652ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.959 ns" { usimplez_cpu:cpu|we_o we_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.959 ns" { usimplez_cpu:cpu|we_o {} we_o {} } { 0.000ns 1.977ns } { 0.000ns 1.982ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}{ "Info" "ITDB_TH_RESULT" "usimplez_cpu:cpu\|data_bus_o\[3\] rst_i clk_i -3.116 ns register " "Info: th for register \"usimplez_cpu:cpu\|data_bus_o\[3\]\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -3.116 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.479 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.618 ns) 2.479 ns usimplez_cpu:cpu\|data_bus_o\[3\] 3 REG LCFF_X31_Y15_N1 1 " "Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu\|data_bus_o\[3\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { clk_i~clkctrl usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.38 % ) " "Info: Total cell delay = 1.472 ns ( 59.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 40.62 % ) " "Info: Total interconnect delay = 1.007 ns ( 40.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|data_bus_o[3] {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.744 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.799 ns) 0.799 ns rst_i 1 PIN PIN_W9 49 " "Info: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_top.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.548ns) + CELL(0.397 ns) 5.744 ns usimplez_cpu:cpu\|data_bus_o\[3\] 2 REG LCFF_X31_Y15_N1 1 " "Info: 2: + IC(4.548 ns) + CELL(0.397 ns) = 5.744 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu\|data_bus_o\[3\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.945 ns" { rst_i usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd" 107 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.196 ns ( 20.82 % ) " "Info: Total cell delay = 1.196 ns ( 20.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.548 ns ( 79.18 % ) " "Info: Total interconnect delay = 4.548 ns ( 79.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" {Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.744 ns" { rst_i usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.744 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|data_bus_o[3] {} } { 0.000ns 0.000ns 4.548ns } { 0.000ns 0.799ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|data_bus_o[3] {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.744 ns" { rst_i usimplez_cpu:cpu|data_bus_o[3] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.744 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|data_bus_o[3] {} } { 0.000ns 0.000ns 4.548ns } { 0.000ns 0.799ns 0.397ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Peak virtual memory: 155 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 11:44:05 2011 " "Info: Processing ended: Wed Nov 09 11:44:05 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}