Subversion Repositories usimplez

|usimplez_top
clk_i => usimplez_cpu:cpu.clk_i
clk_i => usimplez_ram:ram.clk_i
rst_i => usimplez_cpu:cpu.rst_i
we_o <= usimplez_cpu:cpu.we_o
in0_o <= usimplez_cpu:cpu.in0_o
in1_o <= usimplez_cpu:cpu.in1_o
op0_o <= usimplez_cpu:cpu.op0_o
op1_o <= usimplez_cpu:cpu.op1_o


|usimplez_top|usimplez_cpu:cpu
clk_i => Op1_o~reg0.CLK
clk_i => Op0_o~reg0.CLK
clk_i => In1_o~reg0.CLK
clk_i => In0_o~reg0.CLK
clk_i => we_o~reg0.CLK
clk_i => data_bus_o[0]~reg0.CLK
clk_i => data_bus_o[1]~reg0.CLK
clk_i => data_bus_o[2]~reg0.CLK
clk_i => data_bus_o[3]~reg0.CLK
clk_i => data_bus_o[4]~reg0.CLK
clk_i => data_bus_o[5]~reg0.CLK
clk_i => data_bus_o[6]~reg0.CLK
clk_i => data_bus_o[7]~reg0.CLK
clk_i => data_bus_o[8]~reg0.CLK
clk_i => data_bus_o[9]~reg0.CLK
clk_i => data_bus_o[10]~reg0.CLK
clk_i => data_bus_o[11]~reg0.CLK
clk_i => addr_bus_o[0]~reg0.CLK
clk_i => addr_bus_o[1]~reg0.CLK
clk_i => addr_bus_o[2]~reg0.CLK
clk_i => addr_bus_o[3]~reg0.CLK
clk_i => addr_bus_o[4]~reg0.CLK
clk_i => addr_bus_o[5]~reg0.CLK
clk_i => addr_bus_o[6]~reg0.CLK
clk_i => addr_bus_o[7]~reg0.CLK
clk_i => addr_bus_o[8]~reg0.CLK
clk_i => cp_reg_s[0].CLK
clk_i => cp_reg_s[1].CLK
clk_i => cp_reg_s[2].CLK
clk_i => cp_reg_s[3].CLK
clk_i => cp_reg_s[4].CLK
clk_i => cp_reg_s[5].CLK
clk_i => cp_reg_s[6].CLK
clk_i => cp_reg_s[7].CLK
clk_i => cp_reg_s[8].CLK
clk_i => cd_reg_s[0].CLK
clk_i => cd_reg_s[1].CLK
clk_i => cd_reg_s[2].CLK
clk_i => cd_reg_s[3].CLK
clk_i => cd_reg_s[4].CLK
clk_i => cd_reg_s[5].CLK
clk_i => cd_reg_s[6].CLK
clk_i => cd_reg_s[7].CLK
clk_i => cd_reg_s[8].CLK
clk_i => ac_reg_s[0].CLK
clk_i => ac_reg_s[1].CLK
clk_i => ac_reg_s[2].CLK
clk_i => ac_reg_s[3].CLK
clk_i => ac_reg_s[4].CLK
clk_i => ac_reg_s[5].CLK
clk_i => ac_reg_s[6].CLK
clk_i => ac_reg_s[7].CLK
clk_i => ac_reg_s[8].CLK
clk_i => ac_reg_s[9].CLK
clk_i => ac_reg_s[10].CLK
clk_i => ac_reg_s[11].CLK
clk_i => co_reg_s[0].CLK
clk_i => co_reg_s[1].CLK
clk_i => co_reg_s[2].CLK
clk_i => estado~1.DATAIN
rst_i => co_reg_s.OUTPUTSELECT
rst_i => co_reg_s.OUTPUTSELECT
rst_i => co_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => ac_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cd_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => cp_reg_s.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => addr_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => data_bus_o.OUTPUTSELECT
rst_i => we_o.OUTPUTSELECT
rst_i => estado.OUTPUTSELECT
rst_i => estado.OUTPUTSELECT
rst_i => estado.OUTPUTSELECT
rst_i => estado.OUTPUTSELECT
rst_i => In0_o~reg0.ENA
rst_i => In1_o~reg0.ENA
rst_i => Op0_o~reg0.ENA
rst_i => Op1_o~reg0.ENA
data_bus_i[0] => Add2.IN12
data_bus_i[0] => Mux44.IN1
data_bus_i[0] => cd_reg_s.DATAB
data_bus_i[1] => Add2.IN11
data_bus_i[1] => Mux43.IN1
data_bus_i[1] => cd_reg_s.DATAB
data_bus_i[2] => Add2.IN10
data_bus_i[2] => Mux42.IN1
data_bus_i[2] => cd_reg_s.DATAB
data_bus_i[3] => Add2.IN9
data_bus_i[3] => Mux41.IN1
data_bus_i[3] => cd_reg_s.DATAB
data_bus_i[4] => Add2.IN8
data_bus_i[4] => Mux40.IN1
data_bus_i[4] => cd_reg_s.DATAB
data_bus_i[5] => Add2.IN7
data_bus_i[5] => Mux39.IN1
data_bus_i[5] => cd_reg_s.DATAB
data_bus_i[6] => Add2.IN6
data_bus_i[6] => Mux38.IN1
data_bus_i[6] => cd_reg_s.DATAB
data_bus_i[7] => Add2.IN5
data_bus_i[7] => Mux37.IN1
data_bus_i[7] => cd_reg_s.DATAB
data_bus_i[8] => Add2.IN4
data_bus_i[8] => Mux36.IN1
data_bus_i[8] => cd_reg_s.DATAB
data_bus_i[9] => Add2.IN3
data_bus_i[9] => Mux35.IN1
data_bus_i[9] => co_reg_s.DATAB
data_bus_i[10] => Add2.IN2
data_bus_i[10] => Mux34.IN1
data_bus_i[10] => co_reg_s.DATAB
data_bus_i[11] => Add2.IN1
data_bus_i[11] => Mux33.IN1
data_bus_i[11] => co_reg_s.DATAB
data_bus_o[0] <= data_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[1] <= data_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[2] <= data_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[3] <= data_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[4] <= data_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[5] <= data_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[6] <= data_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[7] <= data_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[8] <= data_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[9] <= data_bus_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[10] <= data_bus_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_bus_o[11] <= data_bus_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[0] <= addr_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[1] <= addr_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[2] <= addr_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[3] <= addr_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[4] <= addr_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[5] <= addr_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[6] <= addr_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[7] <= addr_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_bus_o[8] <= addr_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
we_o <= we_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
In0_o <= In0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
In1_o <= In1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
Op0_o <= Op0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
Op1_o <= Op1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE


|usimplez_top|usimplez_ram:ram
clk_i => ram~21.CLK
clk_i => ram~0.CLK
clk_i => ram~1.CLK
clk_i => ram~2.CLK
clk_i => ram~3.CLK
clk_i => ram~4.CLK
clk_i => ram~5.CLK
clk_i => ram~6.CLK
clk_i => ram~7.CLK
clk_i => ram~8.CLK
clk_i => ram~9.CLK
clk_i => ram~10.CLK
clk_i => ram~11.CLK
clk_i => ram~12.CLK
clk_i => ram~13.CLK
clk_i => ram~14.CLK
clk_i => ram~15.CLK
clk_i => ram~16.CLK
clk_i => ram~17.CLK
clk_i => ram~18.CLK
clk_i => ram~19.CLK
clk_i => ram~20.CLK
clk_i => addr_reg_s[0].CLK
clk_i => addr_reg_s[1].CLK
clk_i => addr_reg_s[2].CLK
clk_i => addr_reg_s[3].CLK
clk_i => addr_reg_s[4].CLK
clk_i => addr_reg_s[5].CLK
clk_i => addr_reg_s[6].CLK
clk_i => addr_reg_s[7].CLK
clk_i => addr_reg_s[8].CLK
clk_i => ram.CLK0
addr_i[0] => ram~8.DATAIN
addr_i[0] => addr_reg_s[0].DATAIN
addr_i[0] => ram.WADDR
addr_i[1] => ram~7.DATAIN
addr_i[1] => addr_reg_s[1].DATAIN
addr_i[1] => ram.WADDR1
addr_i[2] => ram~6.DATAIN
addr_i[2] => addr_reg_s[2].DATAIN
addr_i[2] => ram.WADDR2
addr_i[3] => ram~5.DATAIN
addr_i[3] => addr_reg_s[3].DATAIN
addr_i[3] => ram.WADDR3
addr_i[4] => ram~4.DATAIN
addr_i[4] => addr_reg_s[4].DATAIN
addr_i[4] => ram.WADDR4
addr_i[5] => ram~3.DATAIN
addr_i[5] => addr_reg_s[5].DATAIN
addr_i[5] => ram.WADDR5
addr_i[6] => ram~2.DATAIN
addr_i[6] => addr_reg_s[6].DATAIN
addr_i[6] => ram.WADDR6
addr_i[7] => ram~1.DATAIN
addr_i[7] => addr_reg_s[7].DATAIN
addr_i[7] => ram.WADDR7
addr_i[8] => ram~0.DATAIN
addr_i[8] => addr_reg_s[8].DATAIN
addr_i[8] => ram.WADDR8
data_i[0] => ram~20.DATAIN
data_i[0] => ram.DATAIN
data_i[1] => ram~19.DATAIN
data_i[1] => ram.DATAIN1
data_i[2] => ram~18.DATAIN
data_i[2] => ram.DATAIN2
data_i[3] => ram~17.DATAIN
data_i[3] => ram.DATAIN3
data_i[4] => ram~16.DATAIN
data_i[4] => ram.DATAIN4
data_i[5] => ram~15.DATAIN
data_i[5] => ram.DATAIN5
data_i[6] => ram~14.DATAIN
data_i[6] => ram.DATAIN6
data_i[7] => ram~13.DATAIN
data_i[7] => ram.DATAIN7
data_i[8] => ram~12.DATAIN
data_i[8] => ram.DATAIN8
data_i[9] => ram~11.DATAIN
data_i[9] => ram.DATAIN9
data_i[10] => ram~10.DATAIN
data_i[10] => ram.DATAIN10
data_i[11] => ram~9.DATAIN
data_i[11] => ram.DATAIN11
we_i => ram~21.DATAIN
we_i => ram.WE
data_o[0] <= ram.DATAOUT
data_o[1] <= ram.DATAOUT1
data_o[2] <= ram.DATAOUT2
data_o[3] <= ram.DATAOUT3
data_o[4] <= ram.DATAOUT4
data_o[5] <= ram.DATAOUT5
data_o[6] <= ram.DATAOUT6
data_o[7] <= ram.DATAOUT7
data_o[8] <= ram.DATAOUT8
data_o[9] <= ram.DATAOUT9
data_o[10] <= ram.DATAOUT10
data_o[11] <= ram.DATAOUT11