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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.fit.summary] - Rev 3
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Fitter Status : Successful - Wed Nov 09 11:47:37 2011
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : usimplez_top
Top-level Entity Name : usimplez_top
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
Combinational ALUTs : 48 / 12,480 ( < 1 % )
Dedicated logic registers : 63 / 12,480 ( < 1 % )
Total registers : 63
Total pins : 7 / 343 ( 2 % )
Total virtual pins : 0
Total block memory bits : 6,144 / 419,328 ( 1 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )