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Analysis & Synthesis report for usimplez_topWed Nov 09 11:45:57 2011Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Analysis & Synthesis Summary3. Analysis & Synthesis Settings4. Analysis & Synthesis Source Files Read5. Analysis & Synthesis Resource Usage Summary6. Analysis & Synthesis Resource Utilization by Entity7. Analysis & Synthesis RAM Summary8. State Machine - |usimplez_top|usimplez_cpu:cpu|estado9. General Register Statistics10. Registers Packed Into Inferred Megafunctions11. Multiplexer Restructuring Statistics (Restructuring Performed)12. Source assignments for usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated13. Parameter Settings for User Entity Instance: Top-level Entity: |usimplez_top14. Parameter Settings for User Entity Instance: usimplez_cpu:cpu15. Parameter Settings for User Entity Instance: usimplez_ram:ram16. Parameter Settings for Inferred Entity Instance: usimplez_ram:ram|altsyncram:ram_rtl_017. altsyncram Parameter Settings by Entity Instance18. Analysis & Synthesis Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+------------------------------------------------------------------------------+; Analysis & Synthesis Summary ;+-------------------------------+----------------------------------------------+; Analysis & Synthesis Status ; Successful - Wed Nov 09 11:45:57 2011 ;; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;; Revision Name ; usimplez_top ;; Top-level Entity Name ; usimplez_top ;; Family ; Stratix II ;; Logic utilization ; N/A ;; Combinational ALUTs ; 48 ;; Dedicated logic registers ; 63 ;; Total registers ; 63 ;; Total pins ; 7 ;; Total virtual pins ; 0 ;; Total block memory bits ; 6,144 ;; DSP block 9-bit elements ; 0 ;; Total PLLs ; 0 ;; Total DLLs ; 0 ;+-------------------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Settings ;+----------------------------------------------------------------------------+--------------------+--------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------+--------------------+; Top-level entity name ; usimplez_top ; usimplez_top ;; Family name ; Stratix II ; Stratix II ;; Use Generated Physical Constraints File ; Off ; ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Restructure Multiplexers ; Auto ; Auto ;; Create Debugging Nodes for IP Cores ; Off ; Off ;; Preserve fewer node names ; On ; On ;; Disable OpenCore Plus hardware evaluation ; Off ; Off ;; Verilog Version ; Verilog_2001 ; Verilog_2001 ;; VHDL Version ; VHDL_1993 ; VHDL_1993 ;; State Machine Processing ; Auto ; Auto ;; Safe State Machine ; Off ; Off ;; Extract Verilog State Machines ; On ; On ;; Extract VHDL State Machines ; On ; On ;; Ignore Verilog initial constructs ; Off ; Off ;; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;; Add Pass-Through Logic to Inferred RAMs ; On ; On ;; Parallel Synthesis ; On ; On ;; DSP Block Balancing ; Auto ; Auto ;; NOT Gate Push-Back ; On ; On ;; Power-Up Don't Care ; On ; On ;; Remove Redundant Logic Cells ; Off ; Off ;; Remove Duplicate Registers ; On ; On ;; Ignore CARRY Buffers ; Off ; Off ;; Ignore CASCADE Buffers ; Off ; Off ;; Ignore GLOBAL Buffers ; Off ; Off ;; Ignore ROW GLOBAL Buffers ; Off ; Off ;; Ignore LCELL Buffers ; Off ; Off ;; Ignore SOFT Buffers ; On ; On ;; Limit AHDL Integers to 32 Bits ; Off ; Off ;; Optimization Technique ; Balanced ; Balanced ;; Carry Chain Length ; 70 ; 70 ;; Auto Carry Chains ; On ; On ;; Auto Open-Drain Pins ; On ; On ;; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;; Auto ROM Replacement ; On ; On ;; Auto RAM Replacement ; On ; On ;; Auto DSP Block Replacement ; On ; On ;; Auto Shift Register Replacement ; Auto ; Auto ;; Auto Clock Enable Replacement ; On ; On ;; Strict RAM Replacement ; Off ; Off ;; Allow Synchronous Control Signals ; On ; On ;; Force Use of Synchronous Clear Signals ; Off ; Off ;; Auto RAM Block Balancing ; On ; On ;; Auto RAM to Logic Cell Conversion ; Off ; Off ;; Auto Resource Sharing ; Off ; Off ;; Allow Any RAM Size For Recognition ; Off ; Off ;; Allow Any ROM Size For Recognition ; Off ; Off ;; Allow Any Shift Register Size For Recognition ; Off ; Off ;; Use LogicLock Constraints during Resource Balancing ; On ; On ;; Ignore translate_off and synthesis_off directives ; Off ; Off ;; Timing-Driven Synthesis ; Off ; Off ;; Show Parameter Settings Tables in Synthesis Report ; On ; On ;; Ignore Maximum Fan-Out Assignments ; Off ; Off ;; Synchronization Register Chain Length ; 2 ; 2 ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; HDL message level ; Level2 ; Level2 ;; Suppress Register Optimization Related Messages ; Off ; Off ;; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;; Clock MUX Protection ; On ; On ;; Auto Gated Clock Conversion ; Off ; Off ;; Block Design Naming ; Auto ; Auto ;; SDC constraint protection ; Off ; Off ;; Synthesis Effort ; Auto ; Auto ;; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;; Analysis & Synthesis Message Level ; Medium ; Medium ;; Disable Register Merging Across Hierarchies ; Auto ; Auto ;; Resource Aware Inference For Block RAM ; On ; On ;+----------------------------------------------------------------------------+--------------------+--------------------++--------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Source Files Read ;+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+; fibonacci.mif ; yes ; User Memory Initialization File ; C:/Altera/qdesigns/usimplez00/fibonacci.mif ;; usimplez_cpu.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez00/usimplez_cpu.vhd ;; usimplez_ram.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez00/usimplez_ram.vhd ;; usimplez_top.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez00/usimplez_top.vhd ;; altsyncram.tdf ; yes ; Megafunction ; c:/altera/quartus/libraries/megafunctions/altsyncram.tdf ;; db/altsyncram_im61.tdf ; yes ; Auto-Generated Megafunction ; C:/Altera/qdesigns/usimplez00/db/altsyncram_im61.tdf ;+----------------------------------+-----------------+----------------------------------+----------------------------------------------------------++-------------------------------------------------------+; Analysis & Synthesis Resource Usage Summary ;+-----------------------------------------------+-------+; Resource ; Usage ;+-----------------------------------------------+-------+; Estimated ALUTs Used ; 48 ;; Dedicated logic registers ; 63 ;; ; ;; Estimated ALUTs Unavailable ; 1 ;; ; ;; Total combinational functions ; 48 ;; Combinational ALUT usage by number of inputs ; ;; -- 7 input functions ; 1 ;; -- 6 input functions ; 6 ;; -- 5 input functions ; 5 ;; -- 4 input functions ; 0 ;; -- <=3 input functions ; 36 ;; ; ;; Combinational ALUTs by mode ; ;; -- normal mode ; 26 ;; -- extended LUT mode ; 1 ;; -- arithmetic mode ; 21 ;; -- shared arithmetic mode ; 0 ;; ; ;; Estimated ALUT/register pairs used ; 73 ;; ; ;; Total registers ; 63 ;; -- Dedicated logic registers ; 63 ;; -- I/O registers ; 0 ;; ; ;; Estimated ALMs: partially or completely used ; 37 ;; ; ;; I/O pins ; 7 ;; Total block memory bits ; 6144 ;; Maximum fan-out node ; clk_i ;; Maximum fan-out ; 75 ;; Total fan-out ; 603 ;; Average fan-out ; 4.64 ;+-----------------------------------------------+-------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis Resource Utilization by Entity ;+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+; |usimplez_top ; 48 (0) ; 63 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |usimplez_top ; work ;; |usimplez_cpu:cpu| ; 48 (48) ; 63 (63) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_cpu:cpu ; ;; |usimplez_ram:ram| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram ; work ;; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0 ; ;; |altsyncram_im61:auto_generated| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated ; ;+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Analysis & Synthesis RAM Summary ;+---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;+---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 512 ; 12 ; -- ; -- ; 6144 ; fibonacci.mif ;+---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+Encoding Type: One-Hot+----------------------------------------------------------------+; State Machine - |usimplez_top|usimplez_cpu:cpu|estado ;+------------+------------+------------+------------+------------+; Name ; estado.Op1 ; estado.Op0 ; estado.In1 ; estado.In0 ;+------------+------------+------------+------------+------------+; estado.In0 ; 0 ; 0 ; 0 ; 0 ;; estado.In1 ; 0 ; 0 ; 1 ; 1 ;; estado.Op0 ; 0 ; 1 ; 0 ; 1 ;; estado.Op1 ; 1 ; 0 ; 0 ; 1 ;+------------+------------+------------+------------+------------++------------------------------------------------------+; General Register Statistics ;+----------------------------------------------+-------+; Statistic ; Value ;+----------------------------------------------+-------+; Total registers ; 63 ;; Number of registers using Synchronous Clear ; 47 ;; Number of registers using Synchronous Load ; 30 ;; Number of registers using Asynchronous Clear ; 0 ;; Number of registers using Asynchronous Load ; 0 ;; Number of registers using Clock Enable ; 58 ;; Number of registers using Preset ; 0 ;+----------------------------------------------+-------++-----------------------------------------------------------------+; Registers Packed Into Inferred Megafunctions ;+--------------------------------+-------------------------+------+; Register Name ; Megafunction ; Type ;+--------------------------------+-------------------------+------+; usimplez_ram:ram|addr_reg_s[8] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[7] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[6] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[5] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[4] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[3] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[2] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[1] ; usimplez_ram:ram|ram~22 ; RAM ;; usimplez_ram:ram|addr_reg_s[0] ; usimplez_ram:ram|ram~22 ; RAM ;+--------------------------------+-------------------------+------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multiplexer Restructuring Statistics (Restructuring Performed) ;+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+; 3:1 ; 12 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ;; 4:1 ; 12 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ;; 8:1 ; 9 bits ; 45 ALUTs ; 0 ALUTs ; 45 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ;; 10:1 ; 9 bits ; 54 ALUTs ; 18 ALUTs ; 36 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ;; 10:1 ; 12 bits ; 72 ALUTs ; 0 ALUTs ; 72 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0] ;+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------++---------------------------------------------------------------------------------------------+; Source assignments for usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated ;+---------------------------------+--------------------+------+-------------------------------+; Assignment ; Value ; From ; To ;+---------------------------------+--------------------+------+-------------------------------+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;+---------------------------------+--------------------+------+-------------------------------++------------------------------------------------------------------------------+; Parameter Settings for User Entity Instance: Top-level Entity: |usimplez_top ;+----------------+-------+-----------------------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+-----------------------------------------------------+; WIDTH_WORD ; 12 ; Signed Integer ;; WIDTH_ADDRESS ; 9 ; Signed Integer ;+----------------+-------+-----------------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------+; Parameter Settings for User Entity Instance: usimplez_cpu:cpu ;+----------------------+-------+--------------------------------+; Parameter Name ; Value ; Type ;+----------------------+-------+--------------------------------+; width_word ; 12 ; Signed Integer ;; width_operation_code ; 3 ; Signed Integer ;; width_address ; 9 ; Signed Integer ;; st ; 000 ; Unsigned Binary ;; ld ; 001 ; Unsigned Binary ;; add ; 010 ; Unsigned Binary ;; br ; 011 ; Unsigned Binary ;; bz ; 100 ; Unsigned Binary ;; clr ; 101 ; Unsigned Binary ;; dec ; 110 ; Unsigned Binary ;; halt ; 111 ; Unsigned Binary ;+----------------------+-------+--------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+---------------------------------------------------------------+; Parameter Settings for User Entity Instance: usimplez_ram:ram ;+----------------+-------+--------------------------------------+; Parameter Name ; Value ; Type ;+----------------+-------+--------------------------------------+; width_word ; 12 ; Signed Integer ;; width_address ; 9 ; Signed Integer ;+----------------+-------+--------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+----------------------------------------------------------------------------------------+; Parameter Settings for Inferred Entity Instance: usimplez_ram:ram|altsyncram:ram_rtl_0 ;+------------------------------------+----------------------+----------------------------+; Parameter Name ; Value ; Type ;+------------------------------------+----------------------+----------------------------+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;; WIDTH_BYTEENA ; 1 ; Untyped ;; OPERATION_MODE ; SINGLE_PORT ; Untyped ;; WIDTH_A ; 12 ; Untyped ;; WIDTHAD_A ; 9 ; Untyped ;; NUMWORDS_A ; 512 ; Untyped ;; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;; ADDRESS_ACLR_A ; NONE ; Untyped ;; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 1 ; Untyped ;; WIDTHAD_B ; 1 ; Untyped ;; NUMWORDS_B ; 1 ; Untyped ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Untyped ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; AUTO ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;; INIT_FILE ; fibonacci.mif ; Untyped ;; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;; ENABLE_ECC ; FALSE ; Untyped ;; DEVICE_FAMILY ; Stratix II ; Untyped ;; CBXI_PARAMETER ; altsyncram_im61 ; Untyped ;+------------------------------------+----------------------+----------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".+-----------------------------------------------------------------------------------+; altsyncram Parameter Settings by Entity Instance ;+-------------------------------------------+---------------------------------------+; Name ; Value ;+-------------------------------------------+---------------------------------------+; Number of entity instances ; 1 ;; Entity Instance ; usimplez_ram:ram|altsyncram:ram_rtl_0 ;; -- OPERATION_MODE ; SINGLE_PORT ;; -- WIDTH_A ; 12 ;; -- NUMWORDS_A ; 512 ;; -- OUTDATA_REG_A ; UNREGISTERED ;; -- WIDTH_B ; 1 ;; -- NUMWORDS_B ; 1 ;; -- ADDRESS_REG_B ; CLOCK1 ;; -- OUTDATA_REG_B ; UNREGISTERED ;; -- RAM_BLOCK_TYPE ; AUTO ;; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;+-------------------------------------------+---------------------------------------++-------------------------------+; Analysis & Synthesis Messages ;+-------------------------------+Info: *******************************************************************Info: Running Quartus II Analysis & SynthesisInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Wed Nov 09 11:45:48 2011Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez_topInfo: Found 2 design units, including 1 entities, in source file usimplez_cpu.vhdInfo: Found design unit 1: usimplez_cpu-fsmInfo: Found entity 1: usimplez_cpuInfo: Found 2 design units, including 1 entities, in source file usimplez_ram.vhdInfo: Found design unit 1: usimplez_ram-rtlInfo: Found entity 1: usimplez_ramInfo: Found 2 design units, including 1 entities, in source file usimplez_top.vhdInfo: Found design unit 1: usimplez_top-strInfo: Found entity 1: usimplez_topInfo: Elaborating entity "usimplez_top" for the top level hierarchyInfo: Elaborating entity "usimplez_cpu" for hierarchy "usimplez_cpu:cpu"Info: Elaborating entity "usimplez_ram" for hierarchy "usimplez_ram:ram"Info: Inferred 1 megafunctions from design logicInfo: Inferred altsyncram megafunction from the following design logic: "usimplez_ram:ram|ram~22"Info: Parameter OPERATION_MODE set to SINGLE_PORTInfo: Parameter WIDTH_A set to 12Info: Parameter WIDTHAD_A set to 9Info: Parameter NUMWORDS_A set to 512Info: Parameter OUTDATA_REG_A set to UNREGISTEREDInfo: Parameter ADDRESS_ACLR_A set to NONEInfo: Parameter OUTDATA_ACLR_A set to NONEInfo: Parameter INDATA_ACLR_A set to NONEInfo: Parameter WRCONTROL_ACLR_A set to NONEInfo: Parameter INIT_FILE set to fibonacci.mifInfo: Elaborated megafunction instantiation "usimplez_ram:ram|altsyncram:ram_rtl_0"Info: Instantiated megafunction "usimplez_ram:ram|altsyncram:ram_rtl_0" with the following parameter:Info: Parameter "OPERATION_MODE" = "SINGLE_PORT"Info: Parameter "WIDTH_A" = "12"Info: Parameter "WIDTHAD_A" = "9"Info: Parameter "NUMWORDS_A" = "512"Info: Parameter "OUTDATA_REG_A" = "UNREGISTERED"Info: Parameter "ADDRESS_ACLR_A" = "NONE"Info: Parameter "OUTDATA_ACLR_A" = "NONE"Info: Parameter "INDATA_ACLR_A" = "NONE"Info: Parameter "WRCONTROL_ACLR_A" = "NONE"Info: Parameter "INIT_FILE" = "fibonacci.mif"Info: Found 1 design units, including 1 entities, in source file db/altsyncram_im61.tdfInfo: Found entity 1: altsyncram_im61Info: Implemented 94 device resources after synthesis - the final resource count might be differentInfo: Implemented 2 input pinsInfo: Implemented 5 output pinsInfo: Implemented 75 logic cellsInfo: Implemented 12 RAM segmentsInfo: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 194 megabytesInfo: Processing ended: Wed Nov 09 11:45:57 2011Info: Elapsed time: 00:00:09Info: Total CPU time (on all processors): 00:00:08