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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.sim.rpt] - Rev 3
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Simulator report for usimplez_topWed Nov 09 11:48:19 2011Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Simulator Summary3. Simulator Settings4. Simulation Waveforms5. |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM6. Coverage Summary7. Complete 1/0-Value Coverage8. Missing 1-Value Coverage9. Missing 0-Value Coverage10. Simulator INI Usage11. Simulator Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+--------------------------------------------+; Simulator Summary ;+-----------------------------+--------------+; Type ; Value ;+-----------------------------+--------------+; Simulation Start Time ; 0 ps ;; Simulation End Time ; 100.0 us ;; Simulation Netlist Size ; 135 nodes ;; Simulation Coverage ; 89.63 % ;; Total Number of Transitions ; 113971 ;; Simulation Breakpoints ; 0 ;; Family ; Stratix II ;; Device ; EP2S15F484C3 ;+-----------------------------+--------------++-------------------------------------------------------------------------------------------------------------------------+; Simulator Settings ;+--------------------------------------------------------------------------------------------+------------+---------------+; Option ; Setting ; Default Value ;+--------------------------------------------------------------------------------------------+------------+---------------+; Simulation mode ; Timing ; Timing ;; Start time ; 0 ns ; 0 ns ;; Simulation results format ; CVWF ; ;; Add pins automatically to simulation output waveforms ; On ; On ;; Check outputs ; Off ; Off ;; Report simulation coverage ; On ; On ;; Display complete 1/0 value coverage report ; On ; On ;; Display missing 1-value coverage report ; On ; On ;; Display missing 0-value coverage report ; On ; On ;; Detect setup and hold time violations ; Off ; Off ;; Detect glitches ; Off ; Off ;; Disable timing delays in Timing Simulation ; Off ; Off ;; Generate Signal Activity File ; Off ; Off ;; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;; Group bus channels in simulation results ; Off ; Off ;; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;+--------------------------------------------------------------------------------------------+------------+---------------++----------------------+; Simulation Waveforms ;+----------------------+Waveform report data cannot be output to ASCII.Please use Quartus II to view the waveform report data.+-----------------------------------------------------------------------------------------------+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ;+-----------------------------------------------------------------------------------------------+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.+--------------------------------------------------------------------+; Coverage Summary ;+-----------------------------------------------------+--------------+; Type ; Value ;+-----------------------------------------------------+--------------+; Total coverage as a percentage ; 89.63 % ;; Total nodes checked ; 135 ;; Total output ports checked ; 164 ;; Total output ports with complete 1/0-value coverage ; 147 ;; Total output ports with no 1/0-value coverage ; 17 ;; Total output ports with no 1-value coverage ; 17 ;; Total output ports with no 0-value coverage ; 17 ;+-----------------------------------------------------+--------------+The following table displays output ports that toggle between 1 and 0 during simulation.+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Complete 1/0-Value Coverage ;+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+; Node Name ; Output Port Name ; Output Port Type ;+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+; |usimplez_top|usimplez_cpu:cpu|we_o ; |usimplez_top|usimplez_cpu:cpu|we_o ; regout ;; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; regout ;; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[10] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[10] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[4] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[3] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[11] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[11] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[9] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[9] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[6] ; regout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; regout ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; portadataout0 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4 ; portadataout1 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5 ; portadataout2 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6 ; portadataout3 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7 ; portadataout4 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8 ; portadataout5 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9 ; portadataout6 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10 ; portadataout7 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11 ; portadataout8 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; portadataout0 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 ; portadataout1 ;; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2 ; portadataout2 ;; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~3 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~7 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~11 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~15 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~19 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~23 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~27 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~31 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~35 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~39 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~43 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~2 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~6 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~10 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~14 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~18 ; cout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; regout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; regout ;; |usimplez_top|usimplez_cpu:cpu|Selector32~0 ; |usimplez_top|usimplez_cpu:cpu|Selector32~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|In0_o ; |usimplez_top|usimplez_cpu:cpu|In0_o ; regout ;; |usimplez_top|usimplez_cpu:cpu|In1_o ; |usimplez_top|usimplez_cpu:cpu|In1_o ; regout ;; |usimplez_top|usimplez_cpu:cpu|Op0_o ; |usimplez_top|usimplez_cpu:cpu|Op0_o ; regout ;; |usimplez_top|usimplez_cpu:cpu|Op1_o ; |usimplez_top|usimplez_cpu:cpu|Op1_o ; regout ;; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; regout ;; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; regout ;; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; regout ;; |usimplez_top|usimplez_cpu:cpu|estado~6 ; |usimplez_top|usimplez_cpu:cpu|estado~6 ; combout ;; |usimplez_top|usimplez_cpu:cpu|Selector10~0 ; |usimplez_top|usimplez_cpu:cpu|Selector10~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|estado~7 ; |usimplez_top|usimplez_cpu:cpu|estado~7 ; combout ;; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; combout ;; |usimplez_top|usimplez_cpu:cpu|estado~8 ; |usimplez_top|usimplez_cpu:cpu|estado~8 ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; combout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~0 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~1 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~1 ; combout ;; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~2 ; |usimplez_top|usimplez_cpu:cpu|ac_reg_s[0]~2 ; combout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~0 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~0 ; combout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~1 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~1 ; combout ;; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; combout ;; |usimplez_top|we_o ; |usimplez_top|we_o ; padio ;; |usimplez_top|in0_o ; |usimplez_top|in0_o ; padio ;; |usimplez_top|in1_o ; |usimplez_top|in1_o ; padio ;; |usimplez_top|op0_o ; |usimplez_top|op0_o ; padio ;; |usimplez_top|op1_o ; |usimplez_top|op1_o ; padio ;; |usimplez_top|clk_i ; |usimplez_top|clk_i~corein ; combout ;; |usimplez_top|rst_i ; |usimplez_top|rst_i~corein ; combout ;; |usimplez_top|clk_i~clkctrl ; |usimplez_top|clk_i~clkctrl ; outclk ;; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; combout ;; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; combout ;+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+The following table displays output ports that do not toggle to 1 during simulation.+----------------------------------------------------------------------------------------------------------------+; Missing 1-Value Coverage ;+----------------------------------------------+----------------------------------------------+------------------+; Node Name ; Output Port Name ; Output Port Type ;+----------------------------------------------+----------------------------------------------+------------------+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;+----------------------------------------------+----------------------------------------------+------------------+The following table displays output ports that do not toggle to 0 during simulation.+----------------------------------------------------------------------------------------------------------------+; Missing 0-Value Coverage ;+----------------------------------------------+----------------------------------------------+------------------+; Node Name ; Output Port Name ; Output Port Type ;+----------------------------------------------+----------------------------------------------+------------------+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;+----------------------------------------------+----------------------------------------------+------------------++---------------------+; Simulator INI Usage ;+--------+------------+; Option ; Usage ;+--------+------------++--------------------+; Simulator Messages ;+--------------------+Info: *******************************************************************Info: Running Quartus II SimulatorInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Wed Nov 09 11:48:14 2011Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez_topInfo: Using vector source file "C:/Altera/qdesigns/usimplez00/usimplez_top.vwf"Info: Option to preserve fewer signal transitions to reduce memory requirements is enabledInfo: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.Info: Simulation partitioned into 1 sub-simulationsInfo: Simulation coverage is 89.63 %Info: Number of transitions in simulation is 113971Info: Quartus II Simulator was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 121 megabytesInfo: Processing ended: Wed Nov 09 11:48:24 2011Info: Elapsed time: 00:00:10Info: Total CPU time (on all processors): 00:00:10