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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.tan.rpt] - Rev 3
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Classic Timing Analyzer report for usimplez_topWed Nov 09 11:44:05 2011Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Timing Analyzer Summary3. Timing Analyzer Settings4. Clock Settings Summary5. Clock Setup: 'clk_i'6. tsu7. tco8. th9. Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Summary ;+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------+; Worst-case tsu ; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; -- ; clk_i ; 0 ;; Worst-case tco ; N/A ; None ; 6.520 ns ; usimplez_cpu:cpu|we_o ; we_o ; clk_i ; -- ; 0 ;; Worst-case th ; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; -- ; clk_i ; 0 ;; Clock Setup: 'clk_i' ; N/A ; None ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; 0 ;; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+--------------------------------+------------+----------+--------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Settings ;+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+; Option ; Setting ; From ; To ; Entity Name ;+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+; Device Name ; EP2S15F484C3 ; ; ; ;; Timing Models ; Final ; ; ; ;; Default hold multicycle ; Same as Multicycle ; ; ; ;; Cut paths between unrelated clock domains ; On ; ; ; ;; Cut off read during write signal paths ; On ; ; ; ;; Cut off feedback from I/O pins ; On ; ; ; ;; Report Combined Fast/Slow Timing ; Off ; ; ; ;; Ignore Clock Settings ; Off ; ; ; ;; Analyze latches as synchronous elements ; On ; ; ; ;; Enable Recovery/Removal analysis ; Off ; ; ; ;; Enable Clock Latency ; Off ; ; ; ;; Use TimeQuest Timing Analyzer ; Off ; ; ; ;; Number of source nodes to report per destination node ; 10 ; ; ; ;; Number of destination nodes to report ; 10 ; ; ; ;; Number of paths to report ; 200 ; ; ; ;; Report Minimum Timing Checks ; Off ; ; ; ;; Use Fast Timing Models ; Off ; ; ; ;; Report IO Paths Separately ; Off ; ; ; ;; Perform Multicorner Analysis ; On ; ; ; ;; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;; Reports worst-case timing paths for each clock domain and analysis ; Off ; ; ; ;; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;; Output I/O Timing Endpoint ; Near End ; ; ; ;+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Settings Summary ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; clk_i ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Setup: 'clk_i' ;+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.37 MHz ( period = 7.442 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.628 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 134.66 MHz ( period = 7.426 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ; clk_i ; None ; None ; 3.630 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.65 MHz ( period = 7.372 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.593 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 135.94 MHz ( period = 7.356 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ; clk_i ; None ; None ; 3.595 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 136.95 MHz ( period = 7.302 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.558 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 137.25 MHz ( period = 7.286 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ; clk_i ; None ; None ; 3.560 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.27 MHz ( period = 7.232 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.523 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 138.58 MHz ( period = 7.216 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ; clk_i ; None ; None ; 3.525 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.05 MHz ( period = 7.040 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 142.37 MHz ( period = 7.024 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ; clk_i ; None ; None ; 3.429 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.47 MHz ( period = 6.970 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 143.80 MHz ( period = 6.954 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ; clk_i ; None ; None ; 3.394 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 144.93 MHz ( period = 6.900 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 145.26 MHz ( period = 6.884 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ; clk_i ; None ; None ; 3.359 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.41 MHz ( period = 6.830 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 146.76 MHz ( period = 6.814 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.324 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.02 MHz ( period = 6.802 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ; clk_i ; None ; None ; 3.327 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.23 MHz ( period = 6.792 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ; clk_i ; None ; None ; 3.322 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.67 MHz ( period = 6.772 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.312 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; N/A ; 147.84 MHz ( period = 6.764 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ; clk_i ; None ; None ; 3.308 ns ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------++----------------------------------------------------------------------------------------+; tsu ;+-------+--------------+------------+-------+---------------------------------+----------+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;+-------+--------------+------------+-------+---------------------------------+----------+; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;; N/A ; None ; 5.781 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;; N/A ; None ; 5.360 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;; N/A ; None ; 5.309 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;; N/A ; None ; 4.950 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;; N/A ; None ; 4.902 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[3] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[2] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[1] ; clk_i ;; N/A ; None ; 4.631 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[0] ; clk_i ;; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;; N/A ; None ; 4.286 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;; N/A ; None ; 3.762 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;; N/A ; None ; 3.762 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;; N/A ; None ; 3.718 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;; N/A ; None ; 3.718 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;; N/A ; None ; 3.590 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;; N/A ; None ; 3.586 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;; N/A ; None ; 3.586 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;; N/A ; None ; 3.572 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;; N/A ; None ; 3.429 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;+-------+--------------+------------+-------+---------------------------------+----------++---------------------------------------------------------------------------------+; tco ;+-------+--------------+------------+------------------------+-------+------------+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;+-------+--------------+------------+------------------------+-------+------------+; N/A ; None ; 6.520 ns ; usimplez_cpu:cpu|we_o ; we_o ; clk_i ;; N/A ; None ; 6.504 ns ; usimplez_cpu:cpu|In0_o ; in0_o ; clk_i ;; N/A ; None ; 5.960 ns ; usimplez_cpu:cpu|Op0_o ; op0_o ; clk_i ;; N/A ; None ; 5.905 ns ; usimplez_cpu:cpu|In1_o ; in1_o ; clk_i ;; N/A ; None ; 5.701 ns ; usimplez_cpu:cpu|Op1_o ; op1_o ; clk_i ;+-------+--------------+------------+------------------------+-------+------------++----------------------------------------------------------------------------------------------+; th ;+---------------+-------------+-----------+-------+---------------------------------+----------+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;+---------------+-------------+-----------+-------+---------------------------------+----------+; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;; N/A ; None ; -3.116 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;; N/A ; None ; -3.155 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;; N/A ; None ; -3.190 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;; N/A ; None ; -3.236 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;; N/A ; None ; -3.333 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;; N/A ; None ; -3.347 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;; N/A ; None ; -3.351 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;; N/A ; None ; -3.479 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;; N/A ; None ; -3.479 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;; N/A ; None ; -3.523 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;; N/A ; None ; -3.523 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[3] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[4] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[5] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[6] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[7] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[8] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[9] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[10] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[11] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[2] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[1] ; clk_i ;; N/A ; None ; -4.080 ns ; rst_i ; usimplez_cpu:cpu|ac_reg_s[0] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;; N/A ; None ; -4.479 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;+---------------+-------------+-----------+-------+---------------------------------+----------++--------------------------+; Timing Analyzer Messages ;+--------------------------+Info: *******************************************************************Info: Running Quartus II Classic Timing AnalyzerInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Wed Nov 09 11:44:01 2011Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez_topInfo: Started post-fitting delay annotationWarning: Found 5 output pins without output pin load capacitance assignmentInfo: Pin "we_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "in0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "in1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "op0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "op1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyWarning: Found pins functioning as undefined clocks and/or memory enablesInfo: Assuming node "clk_i" is an undefined clockInfo: Clock "clk_i" has Internal fmax of 134.37 MHz between source memory "usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg" and destination register "usimplez_cpu:cpu|ac_reg_s[11]" (period= 7.442 ns)Info: + Longest memory to register delay is 3.628 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg'Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X32_Y15; Fanout = 4; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a1'Info: 3: + IC(0.744 ns) + CELL(0.436 ns) = 3.030 ns; Loc. = LCCOMB_X30_Y14_N2; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~7'Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.065 ns; Loc. = LCCOMB_X30_Y14_N4; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~11'Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.100 ns; Loc. = LCCOMB_X30_Y14_N6; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~15'Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.135 ns; Loc. = LCCOMB_X30_Y14_N8; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~19'Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.170 ns; Loc. = LCCOMB_X30_Y14_N10; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~23'Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 3.205 ns; Loc. = LCCOMB_X30_Y14_N12; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~27'Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 3.301 ns; Loc. = LCCOMB_X30_Y14_N14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~31'Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.336 ns; Loc. = LCCOMB_X30_Y14_N16; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~35'Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 3.371 ns; Loc. = LCCOMB_X30_Y14_N18; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~39'Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 3.406 ns; Loc. = LCCOMB_X30_Y14_N20; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~43'Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 3.531 ns; Loc. = LCCOMB_X30_Y14_N22; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~46'Info: 14: + IC(0.000 ns) + CELL(0.097 ns) = 3.628 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|ac_reg_s[11]'Info: Total cell delay = 2.884 ns ( 79.49 % )Info: Total interconnect delay = 0.744 ns ( 20.51 % )Info: - Smallest clock skew is 0.133 nsInfo: + Shortest clock path from clock "clk_i" to destination register is 2.481 nsInfo: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y14_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|ac_reg_s[11]'Info: Total cell delay = 1.472 ns ( 59.33 % )Info: Total interconnect delay = 1.009 ns ( 40.67 % )Info: - Longest clock path from clock "clk_i" to source memory is 2.348 nsInfo: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'Info: 3: + IC(0.670 ns) + CELL(0.481 ns) = 2.348 ns; Loc. = M4K_X32_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_k961:auto_generated|ram_block1a0~porta_we_reg'Info: Total cell delay = 1.335 ns ( 56.86 % )Info: Total interconnect delay = 1.013 ns ( 43.14 % )Info: + Micro clock to output delay of source is 0.136 nsInfo: + Micro setup delay of destination is 0.090 nsInfo: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by twoInfo: tsu for register "usimplez_cpu:cpu|cp_reg_s[0]" (data pin = "rst_i", clock pin = "clk_i") is 5.781 nsInfo: + Longest pin to register delay is 8.152 nsInfo: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'Info: 2: + IC(4.663 ns) + CELL(0.346 ns) = 5.808 ns; Loc. = LCCOMB_X33_Y14_N30; Fanout = 9; COMB Node = 'usimplez_cpu:cpu|cp_reg_s[6]~1'Info: 3: + IC(1.598 ns) + CELL(0.746 ns) = 8.152 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu|cp_reg_s[0]'Info: Total cell delay = 1.891 ns ( 23.20 % )Info: Total interconnect delay = 6.261 ns ( 76.80 % )Info: + Micro setup delay of destination is 0.090 nsInfo: - Shortest clock path from clock "clk_i" to destination register is 2.461 nsInfo: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X19_Y9_N1; Fanout = 3; REG Node = 'usimplez_cpu:cpu|cp_reg_s[0]'Info: Total cell delay = 1.472 ns ( 59.81 % )Info: Total interconnect delay = 0.989 ns ( 40.19 % )Info: tco from clock "clk_i" to destination pin "we_o" through register "usimplez_cpu:cpu|we_o" is 6.520 nsInfo: + Longest clock path from clock "clk_i" to source register is 2.467 nsInfo: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'Info: 3: + IC(0.652 ns) + CELL(0.618 ns) = 2.467 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu|we_o'Info: Total cell delay = 1.472 ns ( 59.67 % )Info: Total interconnect delay = 0.995 ns ( 40.33 % )Info: + Micro clock to output delay of source is 0.094 nsInfo: + Longest register to pin delay is 3.959 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y14_N1; Fanout = 4; REG Node = 'usimplez_cpu:cpu|we_o'Info: 2: + IC(1.977 ns) + CELL(1.982 ns) = 3.959 ns; Loc. = PIN_B8; Fanout = 0; PIN Node = 'we_o'Info: Total cell delay = 1.982 ns ( 50.06 % )Info: Total interconnect delay = 1.977 ns ( 49.94 % )Info: th for register "usimplez_cpu:cpu|data_bus_o[3]" (data pin = "rst_i", clock pin = "clk_i") is -3.116 nsInfo: + Longest clock path from clock "clk_i" to destination register is 2.479 nsInfo: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|data_bus_o[3]'Info: Total cell delay = 1.472 ns ( 59.38 % )Info: Total interconnect delay = 1.007 ns ( 40.62 % )Info: + Micro hold delay of destination is 0.149 nsInfo: - Shortest pin to register delay is 5.744 nsInfo: 1: + IC(0.000 ns) + CELL(0.799 ns) = 0.799 ns; Loc. = PIN_W9; Fanout = 49; PIN Node = 'rst_i'Info: 2: + IC(4.548 ns) + CELL(0.397 ns) = 5.744 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|data_bus_o[3]'Info: Total cell delay = 1.196 ns ( 20.82 % )Info: Total interconnect delay = 4.548 ns ( 79.18 % )Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warningsInfo: Peak virtual memory: 155 megabytesInfo: Processing ended: Wed Nov 09 11:44:05 2011Info: Elapsed time: 00:00:04Info: Total CPU time (on all processors): 00:00:04