Subversion Repositories v586

# Generated by makeXDC.ulp developed by Sven Raiser, Tuebingen, Germany
#
# Board:     ESA11-7a102t-V1.1.brd
# Part Name: FPGA
# Part pkg:  BGA484
# Memory chip: MT41J128M16JT125K
# Created:   16.11.2015 10:52:19
# Edited:       2016-01-03 by emu

set_property PACKAGE_PIN A1 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN B2 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN D2 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN H3 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN G2 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN F3 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN H2 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN B1 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN E1 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN E2 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN H5 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN D1 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN J5 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN C2 [get_ports {ddr3_addr[13]}]

set_property PACKAGE_PIN F1 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN J2 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN G1 [get_ports {ddr3_ba[2]}]

set_property PACKAGE_PIN G4 [get_ports ddr3_cas_n]

set_property PACKAGE_PIN K2 [get_ports {ddr3_cke[0]}]
set_property PACKAGE_PIN J1 [get_ports {ddr3_ck_n[0]}]
set_property PACKAGE_PIN K1 [get_ports {ddr3_ck_p[0]}]

set_property PACKAGE_PIN J6 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN N4 [get_ports {ddr3_dm[1]}]

set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN K4 [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN J4 [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[7]}]

set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN P6 [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN N2 [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN M5 [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[15]}]

set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN P4 [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN M1 [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN P5 [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN F4 [get_ports {ddr3_odt[0]}]
set_property PACKAGE_PIN H4 [get_ports ddr3_ras_n]
set_property PACKAGE_PIN L6 [get_ports ddr3_reset_n]
set_property PACKAGE_PIN G3 [get_ports ddr3_we_n]

# set_property PACKAGE_PIN N3 [get_ports VREF_DDR]
# set_property IOSTANDARD LVTTL [get_ports VREF_DDR]
# set_property DRIVE 4 [get_ports VREF_DDR]
# set_property PACKAGE_PIN E3 [get_ports VREF_DDR]
# set_property IOSTANDARD LVTTL [get_ports VREF_DDR]
# set_property DRIVE 4 [get_ports VREF_DDR]

#
#       eof
#