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Subversion Repositories v586
[/] [v586/] [trunk/] [board_specific_files/] [nexys4ddr/] [mig.prj] - Rev 121
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<?xml version='1.0' encoding='UTF-8'?><!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --><Project NoOfControllers="1" ><ModuleName>ddr_axi</ModuleName><dci_inouts_inputs>1</dci_inouts_inputs><dci_inputs>1</dci_inputs><Debug_En>OFF</Debug_En><DataDepth_En>1024</DataDepth_En><LowPower_En>ON</LowPower_En><XADC_En>Enabled</XADC_En><TargetFPGA>xc7a100t-csg324/-1</TargetFPGA><Version>3.0</Version><SystemClock>No Buffer</SystemClock><ReferenceClock>No Buffer</ReferenceClock><SysResetPolarity>ACTIVE HIGH</SysResetPolarity><BankSelectionFlag>FALSE</BankSelectionFlag><InternalVref>1</InternalVref><dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs><dci_cascade>0</dci_cascade><Controller number="0" ><MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice><TimePeriod>5000</TimePeriod><VccAuxIO>1.8V</VccAuxIO><PHYRatio>2:1</PHYRatio><InputClkFreq></InputClkFreq><UIExtraClocks>0</UIExtraClocks><MMCM_VCO>1200</MMCM_VCO><MMCMClkOut0> 1.000</MMCMClkOut0><MMCMClkOut1>1</MMCMClkOut1><MMCMClkOut2>1</MMCMClkOut2><MMCMClkOut3>1</MMCMClkOut3><MMCMClkOut4>1</MMCMClkOut4><DataWidth>16</DataWidth><DeepMemory>1</DeepMemory><DataMask>1</DataMask><ECC>Disabled</ECC><Ordering>Normal</Ordering><CustomPart>FALSE</CustomPart><NewPartName></NewPartName><RowAddress>13</RowAddress><ColAddress>10</ColAddress><BankAddress>3</BankAddress><UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap><PinSelection><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" name="ddr2_addr[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" name="ddr2_addr[10]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" name="ddr2_addr[11]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" name="ddr2_addr[12]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" name="ddr2_addr[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" name="ddr2_addr[2]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" name="ddr2_addr[3]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" name="ddr2_addr[4]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" name="ddr2_addr[5]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" name="ddr2_addr[6]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" name="ddr2_addr[7]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" name="ddr2_addr[8]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" name="ddr2_addr[9]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" name="ddr2_ba[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" name="ddr2_ba[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" name="ddr2_ba[2]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" name="ddr2_cas_n" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" name="ddr2_ck_n[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" name="ddr2_ck_p[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" name="ddr2_cke[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" name="ddr2_cs_n[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" name="ddr2_dm[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" name="ddr2_dm[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" name="ddr2_dq[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" name="ddr2_dq[10]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" name="ddr2_dq[11]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" name="ddr2_dq[12]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" name="ddr2_dq[13]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" name="ddr2_dq[14]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" name="ddr2_dq[15]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" name="ddr2_dq[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" name="ddr2_dq[2]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" name="ddr2_dq[3]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" name="ddr2_dq[4]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" name="ddr2_dq[5]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" name="ddr2_dq[6]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" name="ddr2_dq[7]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" name="ddr2_dq[8]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" name="ddr2_dq[9]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" name="ddr2_dqs_n[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" name="ddr2_dqs_n[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" name="ddr2_dqs_p[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" name="ddr2_dqs_p[1]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" name="ddr2_odt[0]" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" name="ddr2_ras_n" IN_TERM="" /><Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" name="ddr2_we_n" IN_TERM="" /></PinSelection><System_Control><Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /><Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /><Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /></System_Control><TimingParameters><Parameters twtr="7.5" trrd="10" trefi="7.8" tfaw="45" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="15" /></TimingParameters><mrBurstLength name="Burst Length" >8</mrBurstLength><mrBurstType name="Burst Type" >Sequential</mrBurstType><mrCasLatency name="CAS Latency" >3</mrCasLatency><mrMode name="Mode" >Normal</mrMode><mrDllReset name="DLL Reset" >No</mrDllReset><mrPdMode name="PD Mode" >Fast exit</mrPdMode><mrWriteRecovery name="Write Recovery" >3</mrWriteRecovery><emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable><emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength><emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection><emrCKSelection name="Memory Clock Selection" >1</emrCKSelection><emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT><emrPosted name="Additive Latency (AL)" >0</emrPosted><emrOCD name="OCD Operation" >OCD Exit</emrOCD><emrDQS name="DQS# Enable" >Enable</emrDQS><emrRDQS name="RDQS Enable" >Disable</emrRDQS><emrOutputs name="Outputs" >Enable</emrOutputs><PortInterface>AXI</PortInterface><AXIParameters><C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM><C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH><C0_S_AXI_DATA_WIDTH>32</C0_S_AXI_DATA_WIDTH><C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH><C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST></AXIParameters></Controller></Project>