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[/] [versatile_fifo/] [trunk/] [backend/] [altera/] [cycloneIV/] [dff_sr.v] - Rev 19
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// megafunction wizard: %LPM_FF% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: lpm_ff // ============================================================ // File Name: dff_sr.v // Megafunction Name(s): // lpm_ff // // Simulation Library Files(s): // lpm // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.1 Build 304 01/25/2010 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module dff_sr ( aclr, aset, clock, data, q); input aclr; input aset; input clock; input data; output q; wire [0:0] sub_wire0; wire [0:0] sub_wire1 = sub_wire0[0:0]; wire q = sub_wire1; wire sub_wire2 = data; wire sub_wire3 = sub_wire2; lpm_ff lpm_ff_component ( .aclr (aclr), .clock (clock), .data (sub_wire3), .aset (aset), .q (sub_wire0) // synopsys translate_off , .aload (), .enable (), .sclr (), .sload (), .sset () // synopsys translate_on ); defparam lpm_ff_component.lpm_fftype = "DFF", lpm_ff_component.lpm_type = "LPM_FF", lpm_ff_component.lpm_width = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACLR NUMERIC "1" // Retrieval info: PRIVATE: ALOAD NUMERIC "0" // Retrieval info: PRIVATE: ASET NUMERIC "1" // Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" // Retrieval info: PRIVATE: CLK_EN NUMERIC "0" // Retrieval info: PRIVATE: DFF NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: PRIVATE: SCLR NUMERIC "0" // Retrieval info: PRIVATE: SLOAD NUMERIC "0" // Retrieval info: PRIVATE: SSET NUMERIC "0" // Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" // Retrieval info: PRIVATE: nBit NUMERIC "1" // Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr // Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data // Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0 // Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE // Retrieval info: LIB_FILE: lpm