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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [versatile_io_module.v] - Rev 11

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`include "versatile_io_defines.v"
`ifdef UART0
    input uart0_rx_pad_i,
    output uart0_tx_pad_o,
`endif
`ifdef UART1
    input uart1_rx_pad_i,
    output uart1_tx_pad_o,
`endif
 

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