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////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, clock and reset //// //// //// //// Description //// //// Logic related to clock and reset //// //// //// //// //// //// To Do: //// //// - add more different registers //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // Global buffer // usage: // use to enable global buffers for high fan out signals such as clock and reset //altera // ALTERA //ACTEL // sync reset // input active lo async reset, normally from external reset generator and/or switch // output active high global reset sync with two DFFs `timescale 1 ns/100 ps module vl_sync_rst ( rst_n_i, rst_o, clk); input rst_n_i, clk; output rst_o; reg [1:0] tmp; always @ (posedge clk or negedge rst_n_i) if (!rst_n_i) tmp <= 2'b11; else tmp <= {1'b0,tmp[0]}; vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); endmodule // vl_pll //altera //actel ////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, registers //// //// //// //// Description //// //// Different type of registers //// //// //// //// //// //// To Do: //// //// - add more different registers //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// module vl_dff ( d, q, clk, rst); parameter width = 1; parameter reset_value = 0; input [width-1:0] d; input clk, rst; output reg [width-1:0] q; always @ (posedge clk or posedge rst) if (rst) q <= reset_value; else q <= d; endmodule module vl_dff_array ( d, q, clk, rst); parameter width = 1; parameter depth = 2; parameter reset_value = 1'b0; input [width-1:0] d; input clk, rst; output [width-1:0] q; reg [0:depth-1] q_tmp [width-1:0]; integer i; always @ (posedge clk or posedge rst) if (rst) begin for (i=0;i<depth;i=i+1) q_tmp[i] <= {width{reset_value}}; end else begin q_tmp[0] <= d; for (i=1;i<depth;i=i+1) q_tmp[i] <= q_tmp[i-1]; end assign q = q_tmp[depth-1]; endmodule module vl_dff_ce ( d, ce, q, clk, rst); parameter width = 1; parameter reset_value = 0; input [width-1:0] d; input ce, clk, rst; output reg [width-1:0] q; always @ (posedge clk or posedge rst) if (rst) q <= reset_value; else if (ce) q <= d; endmodule module vl_dff_ce_clear ( d, ce, clear, q, clk, rst); parameter width = 1; parameter reset_value = 0; input [width-1:0] d; input ce, clear, clk, rst; output reg [width-1:0] q; always @ (posedge clk or posedge rst) if (rst) q <= reset_value; else if (ce) if (clear) q <= {width{1'b0}}; else q <= d; endmodule module vl_dff_ce_set ( d, ce, set, q, clk, rst); parameter width = 1; parameter reset_value = 0; input [width-1:0] d; input ce, set, clk, rst; output reg [width-1:0] q; always @ (posedge clk or posedge rst) if (rst) q <= reset_value; else if (ce) if (set) q <= {width{1'b1}}; else q <= d; endmodule // megafunction wizard: %LPM_FF% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: lpm_ff // ============================================================ // File Name: dff_sr.v // Megafunction Name(s): // lpm_ff // // Simulation Library Files(s): // lpm // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.1 Build 304 01/25/2010 SP 1 SJ Full Version // ************************************************************ //Copyright (C) 1991-2010 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module vl_dff_sr ( aclr, aset, clock, data, q); input aclr; input aset; input clock; input data; output q; wire [0:0] sub_wire0; wire [0:0] sub_wire1 = sub_wire0[0:0]; wire q = sub_wire1; wire sub_wire2 = data; wire sub_wire3 = sub_wire2; lpm_ff lpm_ff_component ( .aclr (aclr), .clock (clock), .data (sub_wire3), .aset (aset), .q (sub_wire0) // synopsys translate_off , .aload (), .enable (), .sclr (), .sload (), .sset () // synopsys translate_on ); defparam lpm_ff_component.lpm_fftype = "DFF", lpm_ff_component.lpm_type = "LPM_FF", lpm_ff_component.lpm_width = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACLR NUMERIC "1" // Retrieval info: PRIVATE: ALOAD NUMERIC "0" // Retrieval info: PRIVATE: ASET NUMERIC "1" // Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" // Retrieval info: PRIVATE: CLK_EN NUMERIC "0" // Retrieval info: PRIVATE: DFF NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: PRIVATE: SCLR NUMERIC "0" // Retrieval info: PRIVATE: SLOAD NUMERIC "0" // Retrieval info: PRIVATE: SSET NUMERIC "0" // Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" // Retrieval info: PRIVATE: nBit NUMERIC "1" // Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr // Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data // Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0 // Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE // Retrieval info: LIB_FILE: lpm // LATCH // For targtes not supporting LATCH use dff_sr with clk=1 and data=1 module vl_latch ( d, le, q, clk); input d, le; output q; input clk; dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); endmodule module vl_shreg ( d, q, clk, rst); parameter depth = 10; input d; output q; input clk, rst; reg [1:depth] dffs; always @ (posedge clk or posedge rst) if (rst) dffs <= {depth{1'b0}}; else dffs <= {d,dffs[1:depth-1]}; assign q = dffs[depth]; endmodule module vl_shreg_ce ( d, ce, q, clk, rst); parameter depth = 10; input d, ce; output q; input clk, rst; reg [1:depth] dffs; always @ (posedge clk or posedge rst) if (rst) dffs <= {depth{1'b0}}; else if (ce) dffs <= {d,dffs[1:depth-1]}; assign q = dffs[depth]; endmodule module vl_delay ( d, q, clk, rst); parameter depth = 10; input d; output q; input clk, rst; reg [1:depth] dffs; always @ (posedge clk or posedge rst) if (rst) dffs <= {depth{1'b0}}; else dffs <= {d,dffs[1:depth-1]}; assign q = dffs[depth]; endmodule module vl_delay_emptyflag ( d, q, emptyflag, clk, rst); parameter depth = 10; input d; output q, emptyflag; input clk, rst; reg [1:depth] dffs; always @ (posedge clk or posedge rst) if (rst) dffs <= {depth{1'b0}}; else dffs <= {d,dffs[1:depth-1]}; assign q = dffs[depth]; assign emptyflag = !(|dffs); endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Logic functions //// //// //// //// Description //// //// Logic functions such as multiplexers //// //// //// //// //// //// To Do: //// //// - //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); parameter width = 32; parameter nr_of_ports = 4; input [width-1:0] a3, a2, a1, a0; input [nr_of_ports-1:0] sel; output [width-1:0] dout; wire [width-1:0] tmp [nr_of_ports-1:0]; integer i; // and assign tmp[0] = {width{sel[0]}} & a0; assign tmp[1] = {width{sel[1]}} & a1; assign tmp[2] = {width{sel[2]}} & a2; assign tmp[3] = {width{sel[3]}} & a3; // or assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0]; endmodule module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); parameter width = 32; parameter nr_of_ports = 5; input [width-1:0] a4, a3, a2, a1, a0; input [nr_of_ports-1:0] sel; output [width-1:0] dout; wire [width-1:0] tmp [nr_of_ports-1:0]; integer i; // and assign tmp[0] = {width{sel[0]}} & a0; assign tmp[1] = {width{sel[1]}} & a1; assign tmp[2] = {width{sel[2]}} & a2; assign tmp[3] = {width{sel[3]}} & a3; assign tmp[4] = {width{sel[4]}} & a4; // or assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; endmodule module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); parameter width = 32; parameter nr_of_ports = 6; input [width-1:0] a5, a4, a3, a2, a1, a0; input [nr_of_ports-1:0] sel; output [width-1:0] dout; wire [width-1:0] tmp [nr_of_ports-1:0]; integer i; // and assign tmp[0] = {width{sel[0]}} & a0; assign tmp[1] = {width{sel[1]}} & a1; assign tmp[2] = {width{sel[2]}} & a2; assign tmp[3] = {width{sel[3]}} & a3; assign tmp[4] = {width{sel[4]}} & a4; assign tmp[5] = {width{sel[5]}} & a5; // or assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0]; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin ( q, rst, clk); parameter length = 4; output [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 0; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else qi <= q_next; assign q = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin_clear ( clear, q, rst, clk); parameter length = 4; input clear; output [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 0; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else qi <= q_next; assign q = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin_ce ( cke, q, rst, clk); parameter length = 4; input cke; output [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 0; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; assign q = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk); parameter length = 4; input clear; input cke; output [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 0; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; assign q = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); parameter length = 4; input clear; input set; input cke; input rew; output [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 0; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next, q_next_fw, q_next_rew; assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1}; assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1}; assign q_next = rew ? q_next_rew : q_next_fw; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; assign q = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // binary counter module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk); parameter length = 4; input cke; input rew; output reg level1; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 1; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next, q_next_fw, q_next_rew; assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; assign q_next_rew = qi - {{length-1{1'b0}},1'b1}; assign q_next = rew ? q_next_rew : q_next_fw; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; always @ (posedge clk or posedge rst) if (rst) level1 <= 1'b0; else if (cke) if (q_next == level1_value) level1 <= 1'b1; else if (qi == level1_value & rew) level1 <= 1'b0; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // LFSR counter module vl_cnt_lfsr_zq ( zq, rst, clk); parameter length = 4; output reg zq; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; reg lfsr_fb; wire [length:1] q_next; reg [32:1] polynom; integer i; always @ (qi) begin case (length) 2: polynom = 32'b11; // 0x3 3: polynom = 32'b110; // 0x6 4: polynom = 32'b1100; // 0xC 5: polynom = 32'b10100; // 0x14 6: polynom = 32'b110000; // 0x30 7: polynom = 32'b1100000; // 0x60 8: polynom = 32'b10111000; // 0xb8 9: polynom = 32'b100010000; // 0x110 10: polynom = 32'b1001000000; // 0x240 11: polynom = 32'b10100000000; // 0x500 12: polynom = 32'b100000101001; // 0x829 13: polynom = 32'b1000000001100; // 0x100C 14: polynom = 32'b10000000010101; // 0x2015 15: polynom = 32'b110000000000000; // 0x6000 16: polynom = 32'b1101000000001000; // 0xD008 17: polynom = 32'b10010000000000000; // 0x12000 18: polynom = 32'b100000010000000000; // 0x20400 19: polynom = 32'b1000000000000100011; // 0x40023 20: polynom = 32'b10000010000000000000; // 0x82000 21: polynom = 32'b101000000000000000000; // 0x140000 22: polynom = 32'b1100000000000000000000; // 0x300000 23: polynom = 32'b10000100000000000000000; // 0x420000 24: polynom = 32'b111000010000000000000000; // 0xE10000 25: polynom = 32'b1001000000000000000000000; // 0x1200000 26: polynom = 32'b10000000000000000000100011; // 0x2000023 27: polynom = 32'b100000000000000000000010011; // 0x4000013 28: polynom = 32'b1100100000000000000000000000; // 0xC800000 29: polynom = 32'b10100000000000000000000000000; // 0x14000000 30: polynom = 32'b100000000000000000000000101001; // 0x20000029 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 default: polynom = 32'b0; endcase lfsr_fb = qi[length]; for (i=length-1; i>=1; i=i-1) begin if (polynom[i]) lfsr_fb = lfsr_fb ~^ qi[i]; end end assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else qi <= q_next; always @ (posedge clk or posedge rst) if (rst) zq <= 1'b1; else zq <= q_next == {length{1'b0}}; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // LFSR counter module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk); parameter length = 4; input cke; output reg zq; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; reg lfsr_fb; wire [length:1] q_next; reg [32:1] polynom; integer i; always @ (qi) begin case (length) 2: polynom = 32'b11; // 0x3 3: polynom = 32'b110; // 0x6 4: polynom = 32'b1100; // 0xC 5: polynom = 32'b10100; // 0x14 6: polynom = 32'b110000; // 0x30 7: polynom = 32'b1100000; // 0x60 8: polynom = 32'b10111000; // 0xb8 9: polynom = 32'b100010000; // 0x110 10: polynom = 32'b1001000000; // 0x240 11: polynom = 32'b10100000000; // 0x500 12: polynom = 32'b100000101001; // 0x829 13: polynom = 32'b1000000001100; // 0x100C 14: polynom = 32'b10000000010101; // 0x2015 15: polynom = 32'b110000000000000; // 0x6000 16: polynom = 32'b1101000000001000; // 0xD008 17: polynom = 32'b10010000000000000; // 0x12000 18: polynom = 32'b100000010000000000; // 0x20400 19: polynom = 32'b1000000000000100011; // 0x40023 20: polynom = 32'b10000010000000000000; // 0x82000 21: polynom = 32'b101000000000000000000; // 0x140000 22: polynom = 32'b1100000000000000000000; // 0x300000 23: polynom = 32'b10000100000000000000000; // 0x420000 24: polynom = 32'b111000010000000000000000; // 0xE10000 25: polynom = 32'b1001000000000000000000000; // 0x1200000 26: polynom = 32'b10000000000000000000100011; // 0x2000023 27: polynom = 32'b100000000000000000000010011; // 0x4000013 28: polynom = 32'b1100100000000000000000000000; // 0xC800000 29: polynom = 32'b10100000000000000000000000000; // 0x14000000 30: polynom = 32'b100000000000000000000000101001; // 0x20000029 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 default: polynom = 32'b0; endcase lfsr_fb = qi[length]; for (i=length-1; i>=1; i=i-1) begin if (polynom[i]) lfsr_fb = lfsr_fb ~^ qi[i]; end end assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; always @ (posedge clk or posedge rst) if (rst) zq <= 1'b1; else if (cke) zq <= q_next == {length{1'b0}}; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // LFSR counter module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); parameter length = 4; input cke; output [length:1] q; output reg zq; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; reg lfsr_fb; wire [length:1] q_next; reg [32:1] polynom; integer i; always @ (qi) begin case (length) 2: polynom = 32'b11; // 0x3 3: polynom = 32'b110; // 0x6 4: polynom = 32'b1100; // 0xC 5: polynom = 32'b10100; // 0x14 6: polynom = 32'b110000; // 0x30 7: polynom = 32'b1100000; // 0x60 8: polynom = 32'b10111000; // 0xb8 9: polynom = 32'b100010000; // 0x110 10: polynom = 32'b1001000000; // 0x240 11: polynom = 32'b10100000000; // 0x500 12: polynom = 32'b100000101001; // 0x829 13: polynom = 32'b1000000001100; // 0x100C 14: polynom = 32'b10000000010101; // 0x2015 15: polynom = 32'b110000000000000; // 0x6000 16: polynom = 32'b1101000000001000; // 0xD008 17: polynom = 32'b10010000000000000; // 0x12000 18: polynom = 32'b100000010000000000; // 0x20400 19: polynom = 32'b1000000000000100011; // 0x40023 20: polynom = 32'b10000010000000000000; // 0x82000 21: polynom = 32'b101000000000000000000; // 0x140000 22: polynom = 32'b1100000000000000000000; // 0x300000 23: polynom = 32'b10000100000000000000000; // 0x420000 24: polynom = 32'b111000010000000000000000; // 0xE10000 25: polynom = 32'b1001000000000000000000000; // 0x1200000 26: polynom = 32'b10000000000000000000100011; // 0x2000023 27: polynom = 32'b100000000000000000000010011; // 0x4000013 28: polynom = 32'b1100100000000000000000000000; // 0xC800000 29: polynom = 32'b10100000000000000000000000000; // 0x14000000 30: polynom = 32'b100000000000000000000000101001; // 0x20000029 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 default: polynom = 32'b0; endcase lfsr_fb = qi[length]; for (i=length-1; i>=1; i=i-1) begin if (polynom[i]) lfsr_fb = lfsr_fb ~^ qi[i]; end end assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; assign q = qi; always @ (posedge clk or posedge rst) if (rst) zq <= 1'b1; else if (cke) zq <= q_next == {length{1'b0}}; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // LFSR counter module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); parameter length = 4; input cke; input rew; output reg level1; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; reg lfsr_fb, lfsr_fb_rew; wire [length:1] q_next, q_next_fw, q_next_rew; reg [32:1] polynom_rew; integer j; reg [32:1] polynom; integer i; always @ (qi) begin case (length) 2: polynom = 32'b11; // 0x3 3: polynom = 32'b110; // 0x6 4: polynom = 32'b1100; // 0xC 5: polynom = 32'b10100; // 0x14 6: polynom = 32'b110000; // 0x30 7: polynom = 32'b1100000; // 0x60 8: polynom = 32'b10111000; // 0xb8 9: polynom = 32'b100010000; // 0x110 10: polynom = 32'b1001000000; // 0x240 11: polynom = 32'b10100000000; // 0x500 12: polynom = 32'b100000101001; // 0x829 13: polynom = 32'b1000000001100; // 0x100C 14: polynom = 32'b10000000010101; // 0x2015 15: polynom = 32'b110000000000000; // 0x6000 16: polynom = 32'b1101000000001000; // 0xD008 17: polynom = 32'b10010000000000000; // 0x12000 18: polynom = 32'b100000010000000000; // 0x20400 19: polynom = 32'b1000000000000100011; // 0x40023 20: polynom = 32'b10000010000000000000; // 0x82000 21: polynom = 32'b101000000000000000000; // 0x140000 22: polynom = 32'b1100000000000000000000; // 0x300000 23: polynom = 32'b10000100000000000000000; // 0x420000 24: polynom = 32'b111000010000000000000000; // 0xE10000 25: polynom = 32'b1001000000000000000000000; // 0x1200000 26: polynom = 32'b10000000000000000000100011; // 0x2000023 27: polynom = 32'b100000000000000000000010011; // 0x4000013 28: polynom = 32'b1100100000000000000000000000; // 0xC800000 29: polynom = 32'b10100000000000000000000000000; // 0x14000000 30: polynom = 32'b100000000000000000000000101001; // 0x20000029 31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 default: polynom = 32'b0; endcase lfsr_fb = qi[length]; for (i=length-1; i>=1; i=i-1) begin if (polynom[i]) lfsr_fb = lfsr_fb ~^ qi[i]; end end assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; always @ (qi) begin case (length) 2: polynom_rew = 32'b11; 3: polynom_rew = 32'b110; 4: polynom_rew = 32'b1100; 5: polynom_rew = 32'b10100; 6: polynom_rew = 32'b110000; 7: polynom_rew = 32'b1100000; 8: polynom_rew = 32'b10111000; 9: polynom_rew = 32'b100010000; 10: polynom_rew = 32'b1001000000; 11: polynom_rew = 32'b10100000000; 12: polynom_rew = 32'b100000101001; 13: polynom_rew = 32'b1000000001100; 14: polynom_rew = 32'b10000000010101; 15: polynom_rew = 32'b110000000000000; 16: polynom_rew = 32'b1101000000001000; 17: polynom_rew = 32'b10010000000000000; 18: polynom_rew = 32'b100000010000000000; 19: polynom_rew = 32'b1000000000000100011; 20: polynom_rew = 32'b10000010000000000000; 21: polynom_rew = 32'b101000000000000000000; 22: polynom_rew = 32'b1100000000000000000000; 23: polynom_rew = 32'b10000100000000000000000; 24: polynom_rew = 32'b111000010000000000000000; 25: polynom_rew = 32'b1001000000000000000000000; 26: polynom_rew = 32'b10000000000000000000100011; 27: polynom_rew = 32'b100000000000000000000010011; 28: polynom_rew = 32'b1100100000000000000000000000; 29: polynom_rew = 32'b10100000000000000000000000000; 30: polynom_rew = 32'b100000000000000000000000101001; 31: polynom_rew = 32'b1001000000000000000000000000000; 32: polynom_rew = 32'b10000000001000000000000000000011; default: polynom_rew = 32'b0; endcase // rotate left polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] }; lfsr_fb_rew = qi[length]; for (i=length-1; i>=1; i=i-1) begin if (polynom_rew[i]) lfsr_fb_rew = lfsr_fb_rew ~^ qi[i]; end end assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]}; assign q_next = rew ? q_next_rew : q_next_fw; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; always @ (posedge clk or posedge rst) if (rst) level1 <= 1'b0; else if (cke) if (q_next == level1_value) level1 <= 1'b1; else if (qi == level1_value & rew) level1 <= 1'b0; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // GRAY counter module vl_cnt_gray ( q, rst, clk); parameter length = 4; output reg [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else qi <= q_next; always @ (posedge clk or posedge rst) if (rst) q <= {length{1'b0}}; else q <= (q_next>>1) ^ q_next; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // GRAY counter module vl_cnt_gray_ce ( cke, q, rst, clk); parameter length = 4; input cke; output reg [length:1] q; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; always @ (posedge clk or posedge rst) if (rst) q <= {length{1'b0}}; else if (cke) q <= (q_next>>1) ^ q_next; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile counter //// //// //// //// Description //// //// Versatile counter, a reconfigurable binary, gray or LFSR //// //// counter //// //// //// //// To Do: //// //// - add LFSR with more taps //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2009 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // GRAY counter module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk); parameter length = 4; input cke; output reg [length:1] q; output [length:1] q_bin; input rst; input clk; parameter clear_value = 0; parameter set_value = 1; parameter wrap_value = 8; parameter level1_value = 15; reg [length:1] qi; wire [length:1] q_next; assign q_next = qi + {{length-1{1'b0}},1'b1}; always @ (posedge clk or posedge rst) if (rst) qi <= {length{1'b0}}; else if (cke) qi <= q_next; always @ (posedge clk or posedge rst) if (rst) q <= {length{1'b0}}; else if (cke) q <= (q_next>>1) ^ q_next; assign q_bin = qi; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, counters //// //// //// //// Description //// //// counters //// //// //// //// //// //// To Do: //// //// - add more counters //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// module vl_cnt_shreg_wrap ( q, rst, clk); parameter length = 4; output reg [0:length-1] q; input rst; input clk; always @ (posedge clk or posedge rst) if (rst) q <= {1'b1,{length-1{1'b0}}}; else q <= {q[length-1],q[0:length-2]}; endmodule module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk); parameter length = 4; input cke; output reg [0:length-1] q; input rst; input clk; always @ (posedge clk or posedge rst) if (rst) q <= {1'b1,{length-1{1'b0}}}; else if (cke) q <= {q[length-1],q[0:length-2]}; endmodule module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk); parameter length = 4; input cke, clear; output reg [0:length-1] q; input rst; input clk; always @ (posedge clk or posedge rst) if (rst) q <= {1'b1,{length-1{1'b0}}}; else if (cke) if (clear) q <= {1'b1,{length-1{1'b0}}}; else q <= q >> 1; endmodule module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk); parameter length = 4; input cke, clear; output reg [0:length-1] q; input rst; input clk; always @ (posedge clk or posedge rst) if (rst) q <= {1'b1,{length-1{1'b0}}}; else if (cke) if (clear) q <= {1'b1,{length-1{1'b0}}}; else q <= {q[length-1],q[0:length-2]}; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, memories //// //// //// //// Description //// //// memories //// //// //// //// //// //// To Do: //// //// - add more memory types //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// /// ROM module vl_rom_init ( adr, q, clk); parameter data_width = 32; parameter addr_width = 8; input [(addr_width-1):0] adr; output reg [(data_width-1):0] q; input clk; reg [data_width-1:0] rom [(1<<addr_width)-1:0]; parameter memory_file = "vl_rom.vmem"; initial begin $readmemh(memory_file, rom); end always @ (posedge clk) q <= rom[adr]; endmodule /* module vl_rom ( adr, q, clk); parameter data_width = 32; parameter addr_width = 4; parameter [0:1>>addr_width-1] data [data_width-1:0] = { {32'h18000000}, {32'hA8200000}, {32'hA8200000}, {32'hA8200000}, {32'h44003000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}, {32'h15000000}}; input [addr_width-1:0] adr; output reg [data_width-1:0] q; input clk; always @ (posedge clk) q <= data[adr]; endmodule */ // Single port RAM module vl_ram ( d, adr, we, q, clk); parameter data_width = 32; parameter addr_width = 8; input [(data_width-1):0] d; input [(addr_width-1):0] adr; input we; output reg [(data_width-1):0] q; input clk; reg [data_width-1:0] ram [(1<<addr_width)-1:0]; parameter init = 0; parameter memory_file = "vl_ram.vmem"; generate if (init) begin : init_mem initial begin $readmemh(memory_file, ram); end end endgenerate always @ (posedge clk) begin if (we) ram[adr] <= d; q <= ram[adr]; end endmodule module vl_ram_be ( d, adr, be, we, q, clk); parameter data_width = 32; parameter addr_width = 8; input [(data_width-1):0] d; input [(addr_width-1):0] adr; input [(addr_width/4)-1:0] be; input we; output reg [(data_width-1):0] q; input clk; reg [data_width-1:0] ram [(1<<addr_width)-1:0]; parameter init = 0; parameter memory_file = "vl_ram.vmem"; generate if (init) begin : init_mem initial begin $readmemh(memory_file, ram); end end endgenerate genvar i; generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram always @ (posedge clk) if (we & be[i]) ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8]; end endgenerate always @ (posedge clk) q <= ram[adr]; endmodule // Dual port RAM // ACTEL FPGA should not use logic to handle rw collision module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); parameter data_width = 32; parameter addr_width = 8; input [(data_width-1):0] d_a; input [(addr_width-1):0] adr_a; input [(addr_width-1):0] adr_b; input we_a; output [(data_width-1):0] q_b; input clk_a, clk_b; reg [(addr_width-1):0] adr_b_reg; reg [data_width-1:0] ram [(1<<addr_width)-1:0] ; parameter init = 0; parameter memory_file = "vl_ram.vmem"; generate if (init) begin : init_mem initial begin $readmemh(memory_file, ram); end end endgenerate always @ (posedge clk_a) if (we_a) ram[adr_a] <= d_a; always @ (posedge clk_b) adr_b_reg <= adr_b; assign q_b = ram[adr_b_reg]; endmodule module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); parameter data_width = 32; parameter addr_width = 8; input [(data_width-1):0] d_a; input [(addr_width-1):0] adr_a; input [(addr_width-1):0] adr_b; input we_a; output [(data_width-1):0] q_b; output reg [(data_width-1):0] q_a; input clk_a, clk_b; reg [(data_width-1):0] q_b; reg [data_width-1:0] ram [(1<<addr_width)-1:0] ; parameter init = 0; parameter memory_file = "vl_ram.vmem"; generate if (init) begin : init_mem initial begin $readmemh(memory_file, ram); end end endgenerate always @ (posedge clk_a) begin q_a <= ram[adr_a]; if (we_a) ram[adr_a] <= d_a; end always @ (posedge clk_b) q_b <= ram[adr_b]; endmodule module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); parameter data_width = 32; parameter addr_width = 8; input [(data_width-1):0] d_a; input [(addr_width-1):0] adr_a; input [(addr_width-1):0] adr_b; input we_a; output [(data_width-1):0] q_b; input [(data_width-1):0] d_b; output reg [(data_width-1):0] q_a; input we_b; input clk_a, clk_b; reg [(data_width-1):0] q_b; reg [data_width-1:0] ram [(1<<addr_width)-1:0] ; parameter init = 0; parameter memory_file = "vl_ram.vmem"; generate if (init) begin : init_mem initial begin $readmemh(memory_file, ram); end end endgenerate always @ (posedge clk_a) begin q_a <= ram[adr_a]; if (we_a) ram[adr_a] <= d_a; end always @ (posedge clk_b) begin q_b <= ram[adr_b]; if (we_b) ram[adr_b] <= d_b; end endmodule // Content addresable memory, CAM // FIFO module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); parameter addr_width = 4; parameter N = addr_width-1; parameter Q1 = 2'b00; parameter Q2 = 2'b01; parameter Q3 = 2'b11; parameter Q4 = 2'b10; parameter going_empty = 1'b0; parameter going_full = 1'b1; input [N:0] wptr, rptr; output fifo_empty; output fifo_full; input wclk, rclk, rst; wire direction; reg direction_set, direction_clr; wire async_empty, async_full; wire fifo_full2; wire fifo_empty2; // direction_set always @ (wptr[N:N-1] or rptr[N:N-1]) case ({wptr[N:N-1],rptr[N:N-1]}) {Q1,Q2} : direction_set <= 1'b1; {Q2,Q3} : direction_set <= 1'b1; {Q3,Q4} : direction_set <= 1'b1; {Q4,Q1} : direction_set <= 1'b1; default : direction_set <= 1'b0; endcase // direction_clear always @ (wptr[N:N-1] or rptr[N:N-1] or rst) if (rst) direction_clr <= 1'b1; else case ({wptr[N:N-1],rptr[N:N-1]}) {Q2,Q1} : direction_clr <= 1'b1; {Q3,Q2} : direction_clr <= 1'b1; {Q4,Q3} : direction_clr <= 1'b1; {Q1,Q4} : direction_clr <= 1'b1; default : direction_clr <= 1'b0; endcase vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); assign async_empty = (wptr == rptr) && (direction==going_empty); assign async_full = (wptr == rptr) && (direction==going_full); vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); /* always @ (posedge wclk or posedge rst or posedge async_full) if (rst) {fifo_full, fifo_full2} <= 2'b00; else if (async_full) {fifo_full, fifo_full2} <= 2'b11; else {fifo_full, fifo_full2} <= {fifo_full2, async_full}; */ /* always @ (posedge rclk or posedge async_empty) if (async_empty) {fifo_empty, fifo_empty2} <= 2'b11; else {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); endmodule // async_comp module vl_fifo_1r1w_async ( d, wr, fifo_full, wr_clk, wr_rst, q, rd, fifo_empty, rd_clk, rd_rst ); parameter data_width = 18; parameter addr_width = 4; // write side input [data_width-1:0] d; input wr; output fifo_full; input wr_clk; input wr_rst; // read side output [data_width-1:0] q; input rd; output fifo_empty; input rd_clk; input rd_rst; wire [addr_width:1] wadr, wadr_bin, radr, radr_bin; vl_cnt_gray_ce_bin # ( .length(addr_width)) fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk)); vl_cnt_gray_ce_bin # (.length(addr_width)) fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk)); vl_dpram_1r1w # (.data_width(data_width), .addr_width(addr_width)) dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk)); vl_fifo_cmp_async # (.addr_width(addr_width)) cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); endmodule module vl_fifo_2r2w_async ( // a side a_d, a_wr, a_fifo_full, a_q, a_rd, a_fifo_empty, a_clk, a_rst, // b side b_d, b_wr, b_fifo_full, b_q, b_rd, b_fifo_empty, b_clk, b_rst ); parameter data_width = 18; parameter addr_width = 4; // a side input [data_width-1:0] a_d; input a_wr; output a_fifo_full; output [data_width-1:0] a_q; input a_rd; output a_fifo_empty; input a_clk; input a_rst; // b side input [data_width-1:0] b_d; input b_wr; output b_fifo_full; output [data_width-1:0] b_q; input b_rd; output b_fifo_empty; input b_clk; input b_rst; vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) vl_fifo_1r1w_async_a ( .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst), .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst) ); vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) vl_fifo_1r1w_async_b ( .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst), .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) ); endmodule module vl_fifo_2r2w_async_simplex ( // a side a_d, a_wr, a_fifo_full, a_q, a_rd, a_fifo_empty, a_clk, a_rst, // b side b_d, b_wr, b_fifo_full, b_q, b_rd, b_fifo_empty, b_clk, b_rst ); parameter data_width = 18; parameter addr_width = 4; // a side input [data_width-1:0] a_d; input a_wr; output a_fifo_full; output [data_width-1:0] a_q; input a_rd; output a_fifo_empty; input a_clk; input a_rst; // b side input [data_width-1:0] b_d; input b_wr; output b_fifo_full; output [data_width-1:0] b_q; input b_rd; output b_fifo_empty; input b_clk; input b_rst; // adr_gen wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin; wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin; // dpram wire [addr_width:0] a_dpram_adr, b_dpram_adr; vl_cnt_gray_ce_bin # ( .length(addr_width)) fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk)); vl_cnt_gray_ce_bin # (.length(addr_width)) fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk)); vl_cnt_gray_ce_bin # ( .length(addr_width)) fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk)); vl_cnt_gray_ce_bin # (.length(addr_width)) fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk)); // mux read or write adr to DPRAM assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin}; assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin}; vl_dpram_2r2w # (.data_width(data_width), .addr_width(addr_width+1)) dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); vl_fifo_cmp_async # (.addr_width(addr_width)) cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) ); vl_fifo_cmp_async # (.addr_width(addr_width)) cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) ); endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, wishbone stuff //// //// //// //// Description //// //// Wishbone compliant modules //// //// //// //// //// //// To Do: //// //// - //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // async wb3 - wb3 bridge `timescale 1ns/1ns module vl_wb3wb3_bridge ( // wishbone slave side wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst, // wishbone master side wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst); input [31:0] wbs_dat_i; input [31:2] wbs_adr_i; input [3:0] wbs_sel_i; input [1:0] wbs_bte_i; input [2:0] wbs_cti_i; input wbs_we_i, wbs_cyc_i, wbs_stb_i; output [31:0] wbs_dat_o; output wbs_ack_o; input wbs_clk, wbs_rst; output [31:0] wbm_dat_o; output reg [31:2] wbm_adr_o; output [3:0] wbm_sel_o; output reg [1:0] wbm_bte_o; output reg [2:0] wbm_cti_o; output reg wbm_we_o; output wbm_cyc_o; output wbm_stb_o; input [31:0] wbm_dat_i; input wbm_ack_i; input wbm_clk, wbm_rst; parameter addr_width = 4; // bte parameter linear = 2'b00; parameter wrap4 = 2'b01; parameter wrap8 = 2'b10; parameter wrap16 = 2'b11; // cti parameter classic = 3'b000; parameter incburst = 3'b010; parameter endofburst = 3'b111; parameter wbs_adr = 1'b0; parameter wbs_data = 1'b1; parameter wbm_adr0 = 2'b00; parameter wbm_adr1 = 2'b01; parameter wbm_data = 2'b10; reg [1:0] wbs_bte_reg; reg wbs; wire wbs_eoc_alert, wbm_eoc_alert; reg wbs_eoc, wbm_eoc; reg [1:0] wbm; wire [1:16] wbs_count, wbm_count; wire [35:0] a_d, a_q, b_d, b_q; wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty; reg a_rd_reg; wire b_rd_adr, b_rd_data; wire b_rd_data_reg; wire [35:0] temp; assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]); always @ (posedge wbs_clk or posedge wbs_rst) if (wbs_rst) wbs_eoc <= 1'b0; else if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) wbs_eoc <= wbs_bte_i==linear; else if (wbs_eoc_alert & (a_rd | a_wr)) wbs_eoc <= 1'b1; vl_cnt_shreg_ce_clear # ( .length(16)) cnt0 ( .cke(wbs_ack_o), .clear(wbs_eoc), .q(wbs_count), .rst(wbs_rst), .clk(wbs_clk)); always @ (posedge wbs_clk or posedge wbs_rst) if (wbs_rst) wbs <= wbs_adr; else if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full) wbs <= wbs_data; else if (wbs_eoc & wbs_ack_o) wbs <= wbs_adr; // wbs FIFO assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i}; assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full : (wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full : 1'b0; assign a_rd = !a_fifo_empty; always @ (posedge wbs_clk or posedge wbs_rst) if (wbs_rst) a_rd_reg <= 1'b0; else a_rd_reg <= a_rd; assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data); assign wbs_dat_o = a_q[35:4]; always @ (posedge wbs_clk or posedge wbs_rst) if (wbs_rst) wbs_bte_reg <= 2'b00; else wbs_bte_reg <= wbs_bte_i; // wbm FIFO assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]); always @ (posedge wbm_clk or posedge wbm_rst) if (wbm_rst) wbm_eoc <= 1'b0; else if (wbm==wbm_adr0 & !b_fifo_empty) wbm_eoc <= b_q[4:3] == linear; else if (wbm_eoc_alert & wbm_ack_i) wbm_eoc <= 1'b1; always @ (posedge wbm_clk or posedge wbm_rst) if (wbm_rst) wbm <= wbm_adr0; else if ((wbm==wbm_adr0 & !b_fifo_empty) | (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) | (wbm==wbm_adr1 & !wbm_we_o) | (wbm==wbm_data & wbm_ack_i & wbm_eoc)) wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10 assign b_d = {wbm_dat_i,4'b1111}; assign b_wr = !wbm_we_o & wbm_ack_i; assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty); assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE] (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 : 1'b0; assign b_rd = b_rd_adr | b_rd_data; vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp; vl_cnt_shreg_ce_clear # ( .length(16)) cnt1 ( .cke(wbm_ack_i), .clear(wbm_eoc), .q(wbm_count), .rst(wbm_rst), .clk(wbm_clk)); assign wbm_cyc_o = wbm==wbm_data; assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty : (wbm==wbm_data) ? 1'b1 : 1'b0; always @ (posedge wbm_clk or posedge wbm_rst) if (wbm_rst) {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic}; else begin if (wbm==wbm_adr0 & !b_fifo_empty) {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q; else if (wbm_eoc_alert & wbm_ack_i) wbm_cti_o <= endofburst; end //async_fifo_dw_simplex_top vl_fifo_2r2w_async_simplex # ( .data_width(36), .addr_width(addr_width)) fifo ( // a side .a_d(a_d), .a_wr(a_wr), .a_fifo_full(a_fifo_full), .a_q(a_q), .a_rd(a_rd), .a_fifo_empty(a_fifo_empty), .a_clk(wbs_clk), .a_rst(wbs_rst), // b side .b_d(b_d), .b_wr(b_wr), .b_fifo_full(b_fifo_full), .b_q(b_q), .b_rd(b_rd), .b_fifo_empty(b_fifo_empty), .b_clk(wbm_clk), .b_rst(wbm_rst) ); endmodule // WB ROM module vl_wb_boot_rom ( wb_adr_i, wb_stb_i, wb_cyc_i, wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst); parameter adr_hi = 31; parameter adr_lo = 28; parameter adr_sel = 4'hf; parameter addr_width = 5; //E2_ifndef BOOT_ROM //E2_define BOOT_ROM "boot_rom.v" //E2_endif input [adr_hi:2] wb_adr_i; input wb_stb_i; input wb_cyc_i; output [31:0] wb_dat_o; output wb_ack_o; output hit_o; input wb_clk; input wb_rst; wire hit; reg [31:0] wb_dat; reg wb_ack; assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel; always @ (posedge wb_clk or posedge wb_rst) if (wb_rst) wb_dat <= 32'h15000000; else case (wb_adr_i[addr_width-1:2]) //E2_include `BOOT_ROM /* // Zero r0 and jump to 0x00000100 0 : wb_dat <= 32'h18000000; 1 : wb_dat <= 32'hA8200000; 2 : wb_dat <= 32'hA8C00100; 3 : wb_dat <= 32'h44003000; 4 : wb_dat <= 32'h15000000; */ default: wb_dat <= 32'h00000000; endcase // case (wb_adr_i) always @ (posedge wb_clk or posedge wb_rst) if (wb_rst) wb_ack <= 1'b0; else wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack; assign hit_o = hit; assign wb_dat_o = wb_dat & {32{wb_ack}}; assign wb_ack_o = wb_ack; endmodule ////////////////////////////////////////////////////////////////////// //// //// //// Arithmetic functions //// //// //// //// Description //// //// Arithmetic functions for ALU and DSP //// //// //// //// //// //// To Do: //// //// - //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // signed multiplication module vl_mults (a,b,p); parameter operand_a_width = 18; parameter operand_b_width = 18; parameter result_hi = 35; parameter result_lo = 0; input [operand_a_width-1:0] a; input [operand_b_width-1:0] b; output [result_hi:result_lo] p; wire signed [operand_a_width-1:0] ai; wire signed [operand_b_width-1:0] bi; wire signed [operand_a_width+operand_b_width-1:0] result; assign ai = a; assign bi = b; assign result = ai * bi; assign p = result[result_hi:result_lo]; endmodule module vl_mults18x18 (a,b,p); input [17:0] a,b; output [35:0] p; vl_mult # (.operand_a_width(18), .operand_b_width(18)) mult0 (.a(a), .b(b), .p(p)); endmodule // unsigned multiplication module vl_mult (a,b,p); parameter operand_a_width = 18; parameter operand_b_width = 18; parameter result_hi = 35; parameter result_lo = 0; input [operand_a_width-1:0] a; input [operand_b_width-1:0] b; output [result_hi:result_hi] p; wire [operand_a_width+operand_b_width-1:0] result; assign result = a * b; assign p = result[result_hi:result_lo]; endmodule // shift unit // supporting the following shift functions // SLL // SRL // SRA module vl_shift_unit_32( din, s, dout, opcode); input [31:0] din; // data in operand input [4:0] s; // shift operand input [1:0] opcode; output [31:0] dout; parameter opcode_sll = 2'b00; //parameter opcode_srl = 2'b01; parameter opcode_sra = 2'b10; //parameter opcode_ror = 2'b11; wire sll, sra; assign sll = opcode == opcode_sll; assign sra = opcode == opcode_sra; wire [15:1] s1; wire [3:0] sign; wire [7:0] tmp [0:3]; // first stage is multiplier based // shift operand as fractional 8.7 assign s1[15] = sll & s[2:0]==3'd7; assign s1[14] = sll & s[2:0]==3'd6; assign s1[13] = sll & s[2:0]==3'd5; assign s1[12] = sll & s[2:0]==3'd4; assign s1[11] = sll & s[2:0]==3'd3; assign s1[10] = sll & s[2:0]==3'd2; assign s1[ 9] = sll & s[2:0]==3'd1; assign s1[ 8] = s[2:0]==3'd0; assign s1[ 7] = !sll & s[2:0]==3'd1; assign s1[ 6] = !sll & s[2:0]==3'd2; assign s1[ 5] = !sll & s[2:0]==3'd3; assign s1[ 4] = !sll & s[2:0]==3'd4; assign s1[ 3] = !sll & s[2:0]==3'd5; assign s1[ 2] = !sll & s[2:0]==3'd6; assign s1[ 1] = !sll & s[2:0]==3'd7; assign sign[3] = din[31] & sra; assign sign[2] = sign[3] & (&din[31:24]); assign sign[1] = sign[2] & (&din[23:16]); assign sign[0] = sign[1] & (&din[15:8]); vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); // second stage is multiplexer based // shift on byte level // mux byte 3 assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] : (sll & s[4:3]==2'b01) ? tmp[2] : (sll & s[4:3]==2'b10) ? tmp[1] : (sll & s[4:3]==2'b11) ? tmp[0] : {8{sign[3]}}; // mux byte 2 assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] : (sll & s[4:3]==2'b01) ? tmp[1] : (sll & s[4:3]==2'b10) ? tmp[0] : (sll & s[4:3]==2'b11) ? {8{1'b0}} : (s[4:3]==2'b01) ? tmp[3] : {8{sign[3]}}; // mux byte 1 assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] : (sll & s[4:3]==2'b01) ? tmp[0] : (sll & s[4:3]==2'b10) ? {8{1'b0}} : (sll & s[4:3]==2'b11) ? {8{1'b0}} : (s[4:3]==2'b01) ? tmp[2] : (s[4:3]==2'b10) ? tmp[3] : {8{sign[3]}}; // mux byte 0 assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] : (sll) ? {8{1'b0}}: (s[4:3]==2'b01) ? tmp[1] : (s[4:3]==2'b10) ? tmp[2] : tmp[3]; endmodule // logic unit // supporting the following logic functions // a and b // a or b // a xor b // not b module vl_logic_unit( a, b, result, opcode); parameter width = 32; parameter opcode_and = 2'b00; parameter opcode_or = 2'b01; parameter opcode_xor = 2'b10; input [width-1:0] a,b; output [width-1:0] result; input [1:0] opcode; assign result = (opcode==opcode_and) ? a & b : (opcode==opcode_or) ? a | b : (opcode==opcode_xor) ? a ^ b : b; endmodule module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl); parameter width = 32; parameter opcode_add = 1'b0; parameter opcode_sub = 1'b1; input [width-1:0] a,b; input c_in, add_sub, sign; output [width-1:0] result; output c_out, z, ovfl; assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))}; assign z = (result=={width{1'b0}}); assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | (~a[width-1] & ~b[width-1] & result[width-1]); endmodule
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