Subversion Repositories versatile_mem_ctrl

Version:8.5.2.4
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
LPM_HINT:TWO
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
DESDIR:L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36
GEN_BEHV_MODULE:T
SMARTGEN_DIE:IS8X8M2
SMARTGEN_PACKAGE:pq208
AGENIII_IS_SUBPROJECT_LIBERO:T
WWIDTH:36
WDEPTH:256
RWIDTH:36
RDEPTH:256
CLKS:2
RESET_POLARITY:2
INIT_RAM:F
DEFAULT_WORD:0x000000000
CASCADE:0
WCLK_EDGE:RISE
RCLK_EDGE:RISE
WCLOCK_PN:WCLK
RCLOCK_PN:RCLK
PMODE2:0
DATA_IN_PN:WD
WADDRESS_PN:WADDR
WE_PN:WEN
DATA_OUT_PN:RD
RADDRESS_PN:RADDR
RE_PN:REN
WE_POLARITY:1
RE_POLARITY:1
PTYPE:1