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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 99

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sdr_sdram_16_ctrl_actel.v:
        vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v

export:
        svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
    
# the single all rule
all: sdr_sdram_16_ctrl_actel.v

clean:
        rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
        rm -rf fifo_fill.v sdr_16.v ddr_16.v
        rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
        rm -rf *_counter.v
        rm -rf *.csv
        rm -rf *~
        rm -rf sdr_sdram_16_ctrl_actel.v

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