Subversion Repositories vg_z80_sbc

# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# Generated Sun Dec  7 17:41:47 2008

filename=wb
intercon=intercon
syscon=syscon
target=generic
hdl=vhdl
signal_groups=0
tga_bits=2
tgc_bits=3
tgd_bits=0
rename_tga=bte
rename_tgc=cti
rename_tgd=tgd
classic=000
endofburst=111
dat_size=32
adr_size=24
mux_type=andor
interconnect=crossbarswitch

master wb32_pci_master
  type=rw
  lock_o=0
  tga_o=0
  tgc_o=0
  tgd_o=0
  err_i=1
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wb_sram=2
  priority_wbs_flash=3
  priority_wbs_ddr=4
  priority_wbs_mmu=5
  priority_wbs_vga=6
  priority_wb_uart0=7
  priority_wb_uart1=8
  priority_wbs_vhdfd=9
  priority_wbs_spimaster=10
  priority_wbs_fpb=11
end master wb32_pci_master

master wbm_z80
  type=rw
  lock_o=0
  tga_o=0
  tgc_o=0
  tgd_o=0
  err_i=0
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wb_sram=2
  priority_wbs_flash=3
  priority_wbs_ddr=4
  priority_wbs_mmu=5
  priority_wbs_vga=6
  priority_wb_uart0=7
  priority_wb_uart1=8
  priority_wbs_vhdfd=9
  priority_wbs_spimaster=10
  priority_wbs_fpb=11
end master wbm_z80

slave wb_cpu_ctrl
  type=rw
  adr_i_hi=2
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x40
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_cpu_ctrl

slave wb_sram
  type=rw
  adr_i_hi=14
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x100000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_sram

slave wbs_flash
  type=rw
  adr_i_hi=18
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x200000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_flash

slave wbs_ddr
  type=rw
  adr_i_hi=19
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x800000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_ddr

slave wbs_mmu
  type=rw
  adr_i_hi=1
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x60
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_mmu

slave wbs_vga
  type=rw
  adr_i_hi=13
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x600000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_vga

slave wb_uart0
  type=rw
  adr_i_hi=2
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x20
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_uart0

slave wb_uart1
  type=rw
  adr_i_hi=4
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x00
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_uart1

slave wbs_vhdfd
  type=rw
  adr_i_hi=2
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0xc0
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_vhdfd

slave wbs_spimaster
  type=rw
  adr_i_hi=5
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x80
  size=0x40
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_spimaster

slave wbs_fpb
  type=rw
  adr_i_hi=4
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0xe0
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_fpb