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URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [vg_s3e_sk/] [vg_s3e_sk.ise] - Rev 35

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PK

__OBJSTORE__/PK
__OBJSTORE__/Autonym/PK
#__OBJSTORE__/ExpandedNetlistEngine/PK
 __OBJSTORE__/HierarchicalDesign/PK
*__OBJSTORE__/HierarchicalDesign/HDProject/PK
__OBJSTORE__/PnAutoRun/PK
__OBJSTORE__/PnAutoRun/Scripts/PK
namespace eval Dpm {
proc GetIseVersion {} {
   set fsetName "fileset.txt"
   set fsetPath ""
   # Find the file in the Xilinx environment.
   # First, construct the environment path.
   set sep ":"; # Default to UNIX style seperator.
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
   }
   set xilinxPath $::env(XILINX)
   if [info exists ::env(MYXILINX)] then {
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
   }
   # Now look in each path of the path until we find a match.
   foreach xilElem [split $xilinxPath $sep] {
      set checkPath ${xilElem}/$fsetName
      set checkPath [ string map { \\ / } $checkPath ]
      if { [file exists $checkPath] } {
         set fsetPath $checkPath
         break
      }
   }
   if { [string equal $fsetPath ""] } {
      puts "ERROR: Can not determine the ISE software version."
      return ""
   }
   if { [catch { open $fsetPath r } fset] } {
      puts "ERROR: Could not open $fsetPath: $fset"
      return ""
   }
   # have the file open, scan for the version entry.
   set sVersion ""
   while { ![eof $fset] } {
      set line [gets $fset]
      regexp {version=(.*)} $line match sVersion
         # The above doesn't stop looking in the file. This assumes that if
         # there are multiple version entries, the last one is the one we want.
   }
   close $fset
   return $sVersion
}
proc CheckForIron {project_name} {
   
   # Determine if the currently running version of ProjNav is earlier than Jade.
   set version [GetIseVersion]
   set dotLocation [string first "." $version]
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
   if {$versionBase < 9} {
      
      # The project file is newer than Iron, so take action to prevent the
      # file from being corrupted.
      # Make the file read-only.
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
         # The above will return 0 for a match to "windows" or "windows64".
         # This is the non-zero part of the if, for lin and sol.
         # Change the permissions to turn off writability.
         file attributes $project_name -permissions a-w
      } else {
         # On Windows, set file to read-only.
         file attributes $project_name -readonly 1
      }      
      
      # And tell the user about it.
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
      # In the console window
      puts $messageText
      # And with a GUI message box if possible.
      ::xilinx::Dpm::TOE::loadGuiLibraries
      set iInterface 0
      set messageDisplay 0
      if {[catch {
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
         set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
         if {$messageDisplay != 0} {
            # Managed to get a component to display a dialog, so use it
            set messageTitle "Incompatible Project Version (Newer)"
            set messageType 2
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
            set messageTimeout 300000
               # in milliseconds, 5 minutes
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
         }
      } catchResult]} {
         # There was an error, probably because we aren't in a GUI enviroment.
      } else {
         # All is well.
      }
      set messageDisplay 0
      set iInterface 0
   }
      
   return 1
}
}
}
::xilinx::Dpm::CheckForIronPK
__OBJSTORE__/ProjectNavigator/PK
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK

=__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap_StrTblPK

}

]
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_sram.xst|PLUGIN_General|1228699794|FILE_XST|Generic||wb_sram.xstwb_sram.xstDESUT_XST|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/wb_sram.stx|PLUGIN_General|1228699795|FILE_XST_STX|Generic||wb_sram.stxwb_sram.stxDESUT_XST_STX|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/wb_sram.prj|PLUGIN_General|1228699794|FILE_XST_PROJECT|Generic||wb_sram.prjwb_sram.prjDESUT_XST_PROJECT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.stx|PLUGIN_General|1228703142||Generic||vg_z80_sbc.stxvg_z80_sbc.stx|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.prm|PLUGIN_General|1228702488|FILE_IMPACT_MISC|Generic||vg_z80_sbc.prmvg_z80_sbc.prmDESUT_IMPACT_MISC|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/wb_mmu.xst|PLUGIN_General|1228440595||Generic||wb_mmu.xstwb_mmu.xst|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/wb_mmu.stx|PLUGIN_General|1228440597||Generic||wb_mmu.stxwb_mmu.stx|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/wb_mmu.prj|PLUGIN_General|1228440595||Generic||wb_mmu.prjwb_mmu.prj|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_impact.log|PLUGIN_General|1228702523|FILE_LOG|Generic||_impact.log_impact.logDESUT_LOG|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_impact.cmd|PLUGIN_General|1228591701|FILE_CMD|Generic||_impact.cmd_impact.cmdDESUT_CMD|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.mcs|PLUGIN_General|1228702488||Generic||vg_z80_sbc.mcsvg_z80_sbc.mcs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/bitgen.xmsgs|PLUGIN_General|1228702292|FILE_XMSGS|Generic||bitgen.xmsgsbitgen.xmsgsDESUT_XMSGS|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.bgn|PLUGIN_General|1228702292|FILE_BITGEN_REPORT|Generic||vg_z80_sbc.bgnvg_z80_sbc.bgnDESUT_BITGEN_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.bit|PLUGIN_General|1228702291|FILE_BIT|Generic||vg_z80_sbc.bitvg_z80_sbc.bitDESUT_BIT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.drc|PLUGIN_General|1228702277|FILE_BITGEN_DRC|Generic||vg_z80_sbc.drcvg_z80_sbc.drcDESUT_BITGEN_DRC|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/trce.xmsgs|PLUGIN_General|1228702269||Generic||trce.xmsgstrce.xmsgs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.twx|PLUGIN_General|1228702269|FILE_TIMING_XML_REPORT|Generic||vg_z80_sbc.twxvg_z80_sbc.twxDESUT_TIMING_XML_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.twr|PLUGIN_General|1228702269|FILE_TIMING_TXT_REPORT|Generic||vg_z80_sbc.twrvg_z80_sbc.twrDESUT_TIMING_TXT_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/par.xmsgs|PLUGIN_General|1228702261||Generic||par.xmsgspar.xmsgs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_pad.csv|PLUGIN_General|1228702259|FILE_PAD_EXCEL_REPORT|Generic||vg_z80_sbc_pad.csvvg_z80_sbc_pad.csvDESUT_PAD_EXCEL_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_pad.txt|PLUGIN_General|1228702259|FILE_PAD_TXT_REPORT|Generic||vg_z80_sbc_pad.txtvg_z80_sbc_pad.txtDESUT_PAD_TXT_REPORTTBIND_viewPadRptsTRAN_viewPadRpts|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_par.xrpt|PLUGIN_General|1228702261|FILE_XRPT|Generic||vg_z80_sbc_par.xrptvg_z80_sbc_par.xrptDESUT_GENERIC|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.xpi|PLUGIN_General|1228702261|FILE_XPI|Generic||vg_z80_sbc.xpivg_z80_sbc.xpiDESUT_XPI|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.unroutes|PLUGIN_General|1228702259|FILE_UNROUTES|Generic||vg_z80_sbc.unroutesvg_z80_sbc.unroutesDESUT_UNROUTES|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.par|PLUGIN_General|1228702261|FILE_PAR_REPORT|Generic||vg_z80_sbc.parvg_z80_sbc.parDESUT_PAR_REPORTTBIND_viewParRptsTRAN_viewParRpts|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.pad|PLUGIN_General|1228702259|FILE_PAD_MISC|Generic||vg_z80_sbc.padvg_z80_sbc.padDESUT_PAD_MISC|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.ncd|PLUGIN_NCD|1228702261|PLUGIN_NCDFILE_NCD|Module||vg_z80_sbcvg_z80_sbcDESUT_NCD|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/map.xmsgs|PLUGIN_General|1228703216||Generic||map.xmsgsmap.xmsgs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_usage.xml|PLUGIN_General|1228703215|FILE_WEBTALK|Generic||vg_z80_sbc_usage.xmlvg_z80_sbc_usage.xml|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_map.ngm|PLUGIN_NGM|1228703163|PLUGIN_NGMFILE_NGMDESUT_NGM3s500efg320-4|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.pcf|PLUGIN_General|1228703211|FILE_PCF|Generic||vg_z80_sbc.pcfvg_z80_sbc.pcfDESUT_PCF|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_map.ncd|PLUGIN_NCD|1228703215||File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_map.xrpt|PLUGIN_General|1228703216||Generic||vg_z80_sbc_map.xrptvg_z80_sbc_map.xrpt|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_map.mrp|PLUGIN_General|1228703216|FILE_MAP_REPORT|Generic||vg_z80_sbc_map.mrpvg_z80_sbc_map.mrpDESUT_MAP_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/ngdbuild.xmsgs|PLUGIN_General|1228703153||Generic||ngdbuild.xmsgsngdbuild.xmsgs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_ngo|PLUGIN_General|1228703147|FILE_DIRECTORY|Generic||_ngo_ngoDESUT_DIRECTORY|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_ngo/netlist.lst|PLUGIN_General|1228703153|FILE_LST|Generic||netlist.lstnetlist.lstDESUT_LST|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.bld|PLUGIN_General|1228703153|FILE_NGDBUILD_LOG|Generic||vg_z80_sbc.bldvg_z80_sbc.bldDESUT_NGDBUILD_LOG|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.ngd|PLUGIN_NGD|1228703153|PLUGIN_NGDFILE_NGDDESUT_NGD|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk_xdb/cst.xbcd|PLUGIN_General|1228702161|FILE_BCD|Generic||cst.xbcdcst.xbcdDESUT_BCD|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/_xmsgs/xst.xmsgs|PLUGIN_General|1228703142||Generic||xst.xmsgsxst.xmsgs|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.cmd_log|PLUGIN_General|1228702810|FILE_CMD_LOG|Generic||vg_z80_sbc.cmd_logvg_z80_sbc.cmd_logDESUT_CMD_LOG|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/xst|PLUGIN_General|1228423638||Generic||xstxst|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.ngr|PLUGIN_NGR|1228702891|PLUGIN_NGRFILE_NGRDESUT_NGR|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.ngc|PLUGIN_NGC|1228703141|PLUGIN_NGCFILE_NGCDESUT_NGCxc3s500e-4-fg320|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_vhdl.prj|PLUGIN_General|1228702812||Generic||vg_z80_sbc_vhdl.prjvg_z80_sbc_vhdl.prj|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.prj|PLUGIN_General|1228702810||Generic||vg_z80_sbc.prjvg_z80_sbc.prj|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.syr|PLUGIN_General|1228703142|FILE_XST_REPORT|Generic||vg_z80_sbc.syrvg_z80_sbc.syrDESUT_XST_REPORT|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.lso|PLUGIN_General|1228423636|FILE_LSO|Generic||vg_z80_sbc.lsovg_z80_sbc.lsoDESUT_LSO|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.xst|PLUGIN_General|1228702810||Generic||vg_z80_sbc.xstvg_z80_sbc.xst|File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc_guide.ncd|PLUGIN_NCD|1228702261||File||C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.ucf|PLUGIN_AssocModule|1228625559|PLUGIN_AssocModuleFILE_UCF|Module||vg_z80_sbc.ucfvg_z80_sbc.ucfDESUT_UCF|File||C:/opencores/vg_z80_sbc/rtl/z80_memstate2.v|PLUGIN_Verilog|1228096810|FILE_VERILOG|Module||z80_memstate2z80_memstate2DESUT_VERILOG|File||C:/opencores/vg_z80_sbc/rtl/z80_inst_exec.v|PLUGIN_Verilog|1228096810||Module||z80_inst_execz80_inst_exec|File||C:/opencores/vg_z80_sbc/rtl/z80_core_top.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||z80_core_top|z80_core_top|i_z80_inst_exec|z80_inst_exec||ComponentInstantiation||z80_core_top|z80_core_top|i_z80_memstate2|z80_memstate2||Module||z80_core_topz80_core_topi_z80_inst_execi_z80_memstate2|File||C:/opencores/vg_z80_sbc/rtl/wb_vhdfd.v|PLUGIN_Verilog|1228702789||ComponentInstantiation||wb_vhdfd|wb_vhdfd|disks|vhdfd_disk||ComponentInstantiation||wb_vhdfd|wb_vhdfd|sector_ram|vga_dpram||Module||vhdfd_disk|Module||wb_vhdfdvhdfd_diskwb_vhdfdsector_ramvga_dpramdisks|File||C:/opencores/vg_z80_sbc/rtl/wb_vga.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||wb_vga|wb_vga|font_ram|vga_dpram||ComponentInstantiation||wb_vga|wb_vga|vga_controller|vga80x40||ComponentInstantiation||wb_vga|wb_vga|video_ram|vga_dpram||Module||wb_vgawb_vgafont_ramvideo_ramvga_controllervga80x40|File||C:/opencores/vg_z80_sbc/rtl/wb_uart.v|PLUGIN_Verilog|1228500078||ComponentInstantiation||wb_uart|wb_uart|ps2_kbd|ps2_keyboard_interface||ComponentInstantiation||wb_uart|wb_uart|uart1|uart||ComponentInstantiation||wb_uart|wb_uart|uart2|uart||ComponentInstantiation||wb_uart|wb_uart|uart3|uart||Module||wb_uartwb_uartuart3uartuart2uart1ps2_kbdps2_keyboard_interface|File||C:/opencores/vg_z80_sbc/rtl/wb_sram.v|PLUGIN_Verilog|1228702159||ComponentInstantiation||wb_sram|wb_sram|sram_block0|sram_block||Module||sram_block|Module||wb_sramsram_blockwb_sramsram_block0|File||C:/opencores/vg_z80_sbc/rtl/wb_mmu.v|PLUGIN_Verilog|1228702030||Module||wb_mmuwb_mmu|File||C:/opencores/vg_z80_sbc/rtl/wb_flash.v|PLUGIN_Verilog|1228230937||Module||wb_flashwb_flash|File||C:/opencores/vg_z80_sbc/rtl/wb_ddr.v|PLUGIN_Verilog|1228345332||ComponentInstantiation||wb_ddr|wb_ddr|ctrl0|ddr_ctrl||ComponentInstantiation||wb_ddr|wb_ddr|tag_ram|dpram||ComponentInstantiation||wb_ddr|wb_ddr|way0_ram|dpram||ComponentInstantiation||wb_ddr|wb_ddr|way1_ram|dpram||Module||wb_ddrwb_ddrctrl0ddr_ctrlway1_ramdpramway0_ramtag_ram|File||C:/opencores/vg_z80_sbc/rtl/wb_cpu_ctrl.v|PLUGIN_Verilog|1228096810||Module||wb_cpu_ctrlwb_cpu_ctrl|File||C:/opencores/vg_z80_sbc/rtl/wb.vhd|PLUGIN_Vhdl|1228700507|FILE_VHDL|Architecture||rtl|intercon|||Architecture||rtl|trafic_supervision|||EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision|||EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(1)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(10)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(2)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(3)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(4)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(5)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(6)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(7)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(8)|EntityInstantiation||intercon|rtl|trafic_supervision_1|work.trafic_supervision||-Instance(9)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision|||EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(1)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(10)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(2)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(3)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(4)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(5)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(6)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(7)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(8)|EntityInstantiation||intercon|rtl|trafic_supervision_2|work.trafic_supervision||-Instance(9)|Entity||intercon|Entity||trafic_supervision|Library||||Library|||-Instance(1)|Library|||-Instance(2)|PackageBody||intercon_package||PackageDecl||intercon_package||Use||IEEE|std_logic_1164|all||Use||IEEE|std_logic_1164|all|-Instance(1)|Use||IEEE|std_logic_1164|all|-Instance(2)|Use||work|intercon_package|all|rtlinterconDESUT_VHDL_ARCHITECTUREtrafic_supervision_2work.trafic_supervisiontrafic_supervision_1DESUT_VHDL_ENTITYwork.intercon_package.allintercon_packageallIEEE.std_logic_1164.allIEEEstd_logic_1164trafic_supervisionDESUT_VHDL_PACKAGE_BODYDESUT_VHDL_PACKAGE_DECL|File||C:/opencores/vg_z80_sbc/rtl/vga_dpram.v|PLUGIN_Verilog|1228096810||Module||vga_dpram|File||C:/opencores/vg_z80_sbc/rtl/vga80x40.vhd|PLUGIN_Vhdl|1228096810||Architecture||rtl|vga80x40|||ComponentInstantiation||vga80x40|rtl|U_CHRX|ctrm||ComponentInstantiation||vga80x40|rtl|U_CHRY|ctrm||ComponentInstantiation||vga80x40|rtl|U_HCTR|ctrm||ComponentInstantiation||vga80x40|rtl|U_LOSR|losr||ComponentInstantiation||vga80x40|rtl|U_SCRX|ctrm||ComponentInstantiation||vga80x40|rtl|U_SCRY|ctrm||ComponentInstantiation||vga80x40|rtl|U_VCTR|ctrm||Entity||vga80x40|Use||ieee|numeric_std|all||Use||ieee|std_logic_1164|all|U_LOSRlosrU_SCRYctrmU_SCRXU_CHRYU_CHRXU_VCTRU_HCTRieee.numeric_std.allieeenumeric_stdieee.std_logic_1164.all|File||C:/opencores/vg_z80_sbc/rtl/uart_wb.v|PLUGIN_Verilog|1228096810||Module||uart_wbuart_wb|File||C:/opencores/vg_z80_sbc/rtl/uart_transmitter.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_transmitter|uart_transmitter|fifo_tx|uart_tfifo||Module||uart_transmitteruart_transmitterfifo_txuart_tfifo|File||C:/opencores/vg_z80_sbc/rtl/uart_top.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_top|uart_top|dbg|uart_debug_if||ComponentInstantiation||uart_top|uart_top|regs|uart_regs||ComponentInstantiation||uart_top|uart_top|wb_interface|uart_wb||Module||uart_topuart_topdbguart_debug_ifregsuart_regswb_interface|File||C:/opencores/vg_z80_sbc/rtl/uart_tfifo.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_tfifo|uart_tfifo|tfifo|raminfr||Module||uart_tfifotfiforaminfr|File||C:/opencores/vg_z80_sbc/rtl/uart_sync_flops.v|PLUGIN_Verilog|1228096810||Module||uart_sync_flopsuart_sync_flops|File||C:/opencores/vg_z80_sbc/rtl/uart_rfifo.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_rfifo|uart_rfifo|rfifo|raminfr||Module||uart_rfifouart_rfiforfifo|File||C:/opencores/vg_z80_sbc/rtl/uart_regs.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_regs|uart_regs|i_uart_sync_flops|uart_sync_flops||ComponentInstantiation||uart_regs|uart_regs|receiver|uart_receiver||ComponentInstantiation||uart_regs|uart_regs|transmitter|uart_transmitter||Module||uart_regsreceiveruart_receiveri_uart_sync_flopstransmitter|File||C:/opencores/vg_z80_sbc/rtl/uart_receiver.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||uart_receiver|uart_receiver|fifo_rx|uart_rfifo||Module||uart_receiverfifo_rx|File||C:/opencores/vg_z80_sbc/rtl/uart_defines.v|PLUGIN_Verilog|1228096810||File||C:/opencores/vg_z80_sbc/rtl/uart_debug_if.v|PLUGIN_Verilog|1228096810||Module||uart_debug_if|File||C:/opencores/vg_z80_sbc/rtl/uart.v|PLUGIN_Verilog|1228096810||Module||uart|File||C:/opencores/vg_z80_sbc/rtl/top_vg_z80.v|PLUGIN_Verilog|1228702544||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|cpu_ctrl0|wb_cpu_ctrl||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|cpu_ctrl1|wb_cpu_ctrl||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|cpu_ctrl2|wb_cpu_ctrl||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|mmu0|wb_mmu||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|sram0|wb_sram||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|sram1|wb_sram||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|sram2|wb_sram||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|uart0|uart_top||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|vfdhd0|wb_vhdfd||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|vga0|wb_vga||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|wb_intercon|intercon||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|wb_uart1|wb_uart||ComponentInstantiation||vg_z80_sbc|vg_z80_sbc|z80cpu|z80_core_top|wb_interconcpu_ctrl2cpu_ctrl1vfdhd0mmu0sram1sram2wb_uart1uart0vga0sram0cpu_ctrl0z80cpu|File||C:/opencores/vg_z80_sbc/rtl/timescale.v|PLUGIN_Verilog|1228096810||File||C:/opencores/vg_z80_sbc/rtl/rotary.v|PLUGIN_Verilog|1228096810||Module||rotaryrotary|File||C:/opencores/vg_z80_sbc/rtl/raminfr.v|PLUGIN_Verilog|1228096810||Module||raminfr|File||C:/opencores/vg_z80_sbc/rtl/ps2.v|PLUGIN_Verilog|1228096810||Module||ps2_keyboard_interface|File||C:/opencores/vg_z80_sbc/rtl/opcodes.v|PLUGIN_Verilog|1228096810||File||C:/opencores/vg_z80_sbc/rtl/losr.vhd|PLUGIN_Vhdl|1228096810||Architecture||arch|losr|||Entity||losr|Use||ieee|std_logic_arith|all||Use||ieee|std_logic_unsigned|all|archieee.std_logic_unsigned.allstd_logic_unsignedieee.std_logic_arith.allstd_logic_arith|File||C:/opencores/vg_z80_sbc/rtl/gray_counter.v|PLUGIN_Verilog|1228096810||Module||GrayCounterGrayCounter|File||C:/opencores/vg_z80_sbc/rtl/dpram.v|PLUGIN_Verilog|1228096810||Module||dpram|File||C:/opencores/vg_z80_sbc/rtl/ddr_wpath.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||ddr_wpath|ddr_wpath|cba_fifo|async_fifo||ComponentInstantiation||ddr_wpath|ddr_wpath|wdata_fifo|async_fifo||Module||ddr_wpathddr_wpathwdata_fifoasync_fifocba_fifo|File||C:/opencores/vg_z80_sbc/rtl/ddr_rpath.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||ddr_rpath|ddr_rpath|rfifo|async_fifo||Module||ddr_rpathddr_rpath|File||C:/opencores/vg_z80_sbc/rtl/ddr_pulse78.v|PLUGIN_Verilog|1228096810||Module||ddr_pulse78ddr_pulse78|File||C:/opencores/vg_z80_sbc/rtl/ddr_init.v|PLUGIN_Verilog|1228096810||Module||ddr_initddr_init|File||C:/opencores/vg_z80_sbc/rtl/ddr_include.v|PLUGIN_Verilog|1228345132||File||C:/opencores/vg_z80_sbc/rtl/ddr_ctrl.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||ddr_ctrl|ddr_ctrl|clkgen|ddr_clkgen||ComponentInstantiation||ddr_ctrl|ddr_ctrl|init|ddr_init||ComponentInstantiation||ddr_ctrl|ddr_ctrl|pulse79_gen|ddr_pulse78||ComponentInstantiation||ddr_ctrl|ddr_ctrl|rpath0|ddr_rpath||ComponentInstantiation||ddr_ctrl|ddr_ctrl|wpath0|ddr_wpath||Module||ddr_ctrlinitpulse79_genrpath0wpath0clkgenddr_clkgen|File||C:/opencores/vg_z80_sbc/rtl/ddr_clkgen.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||ddr_clkgen|ddr_clkgen|rotdec0|rotary||Module||ddr_clkgenrotdec0|File||C:/opencores/vg_z80_sbc/rtl/ctrm.vhd|PLUGIN_Vhdl|1228096810||Architecture||arch|ctrm|||Entity||ctrm|File||C:/opencores/vg_z80_sbc/rtl/async_fifo.v|PLUGIN_Verilog|1228096810||ComponentInstantiation||async_fifo|async_fifo|GrayCounter_pRd|GrayCounter||ComponentInstantiation||async_fifo|async_fifo|GrayCounter_pWr|GrayCounter||Module||async_fifoGrayCounter_pRdGrayCounter_pWrAutoGeneratedViewVIEW_AssignPackagePinsTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_XSTPreSynthesisTBINDEXT_XSTPreSynthesisToStructural_spartan3eTRAN_SubProjectPreToStructuralProxyModule|vg_z80_sbcTRAN_compileBCD2trueNoHigh<>AllClockNetsAutoYesfalseSpeed500As OptimizedMaintainHDL10024./xstLUT/xc3s500eNone-4fg320XST (VHDL/Verilog)TRANEXT_xstsynthesize_spartan3eVIEW_StructuralTBIND_StructuralToPost-SynthesisAbstractSimulationTRAN_postSynthesisSimModelVIEW_Post-SynthesisAbstractSimulationTBINDEXT_StructuralToTranslation_FPGAOffTimestampTRANEXT_ngdbuild_FPGAVIEW_TranslationTBIND_xlateFloorPlannerTRAN_xlateFloorPlannerVIEW_Post-TranslateFloorPlannerTBIND_xlateAssignPackagePinsTRAN_xlateAssignPackagePinsVIEW_Post-TranslateAssignPinsTBIND_TranslationToPost-TranslateFormalityNetlistTRAN_postXlateFormalityNetlistVIEW_Post-TranslateFormalityNetlistTBIND_TranslationToPost-TranslateAbstractSimulationTRAN_postXlateSimModelVIEW_Post-TranslateAbstractSimulationTBIND_Post-TranslateAbstractToTBWPreSimulationTRAN_createPostXlateTestBenchTRAN_copyPost-TranslateAbstractToPreSimulationVIEW_TBWPost-TranslatePreSimulationTBIND_Post-TranslateAbstractToPreSimulationVIEW_Post-TranslatePreSimulationTBIND_TranslateToSmartTRAN_CopySmartXplorerResultTRAN_SmartXplorerVIEW_SmartXplorerTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_FloorplanDesignTRAN_floorplanDesignVIEW_Post-TranslateFloorplanDesignTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToMap_spartan3Normal4Area1For Inputs and OutputsTRANEXT_map_spartan3VIEW_MapTBIND_preRouteTrceTRAN_preRouteTrceVIEW_Post-MapStaticTimingTBIND_mapFpgaEditorTRAN_mapFpgaEditorVIEW_Post-MapFpgaEditorTBIND_mapFloorPlannerTRAN_mapFloorPlannerVIEW_Post-MapFloorPlannerTBIND_MapToPost-MapAbstractSimulationTRAN_postMapSimModelVIEW_Post-MapAbstractSimulationTBIND_Post-MapAbstractToTBWPreSimulationTRAN_createPostMapTestBenchTRAN_copyPost-MapAbstractToPreSimulationVIEW_TBWPost-MapPreSimulationTBIND_Post-MapAbstractToPreSimulationVIEW_Post-MapPreSimulationTBINDEXT_MapToPar_spartan3Normal Place and RouteTRANEXT_par_spartan3VIEW_ParTBIND_postRouteTrceError Report3TRAN_postRouteTrceVIEW_Post-ParStaticTimingTBIND_postParPrimetimeNetlistTRAN_postParPrimetimeNetlistVIEW_PrimetimeNetlistTBIND_parFpgaEditorTRAN_parFpgaEditorVIEW_Post-ParFpgaEditorTBIND_parFloorPlannerTRAN_parFloorPlannerVIEW_Post-ParFloorPlannerTBIND_genPowerDataTRAN_genPowerDataVIEW_FPGAGeneratePowerDataTBIND_createIBISModelTRAN_createIBISModelVIEW_IBISModelTBIND_XpowerTRAN_XPowerVIEW_FPGAAnalyzePowerTBIND_ParToPost-ParFormalityNetlistTRAN_postParFormalityNetlistVIEW_Post-ParFormalityNetlistTBIND_ParToPost-ParClockRegionTRAN_clkRegionRptVIEW_Post-ParClockRegionReportTBIND_ParToPost-ParAsyncDelayTRAN_asynDlyRptVIEW_Post-ParAsyncDelayReportTBIND_ParToPost-ParAbstractSimulationTRAN_postParSimModelVIEW_Post-ParAbstractSimulationTBIND_Post-ParAbstractToTBWPreSimulationTRAN_createPostParTestBenchTRAN_copyPost-ParAbstractToPreSimulationVIEW_TBWPost-ParPreSimulationTBIND_TBWPost-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuse(bencher)VIEW_TBWPost-ParFuseTBIND_TBWPost-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModel(bencher)VIEW_TBWPost-ParSimulationISimTBIND_Post-ParAbstractToPreSimulationVIEW_Post-ParPreSimulationTBIND_Post-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuseVIEW_Post-ParFuseTBIND_Post-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModelVIEW_Post-ParSimulationISimTBIND_ParToMpprResultTRAN_copyMpprRsltVIEW_MpprResultTBIND_ParToLockedPinConstraintsTRAN_genLockedPinConstraintsVIEW_LockedPinConstraintsTBIND_ParToBackAnnoPinLocationsTRAN_backAnnoPinLocationsVIEW_BackAnnoPinLocationsTBINDEXT_ParToFPGAConfiguration_spartan3ePull UpEnable Readback and ReconfigurationDefault (1)CCLKDefault (4)Default (NoWait)Default (6)Default (5)Pull Down0xFFFFFFFFTRANEXT_bitFile_spartan3eVIEW_FPGAConfigurationTBIND_analyzeDesignUsingChipscopeTRAN_analyzeDesignUsingChipscopeVIEW_AnalyzedDesignTBIND_UpdateBitstreamXPSTRAN_xpsUpdBitstreamVIEW_UpdatedBitstreamTBIND_FPGAConfigurationToFPGAGeneratePROMTRAN_genImpactFileVIEW_FPGAGeneratePROMTBIND_FPGAConfigurationToFPGAConfigureTargetDeviceDefaultAuto - defaultTRAN_configureTargetDeviceVIEW_FPGAConfigureTargetDeviceTBIND_FPGAConfigurationToFPGAConfigureDeviceTRAN_impactProgrammingToolVIEW_FPGAConfigureDeviceTBIND_XSTAbstractToPreSynthesisTRAN_SubProjectAbstractToPreProxyTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_XSTAbstractSynthesis/vg_z80_sbcTBIND_InitialToXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_AbstractSimulationTBIND_AbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_FPGATRANEXT_compLibraries_FPGAVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguageVerilogPROP_SimulatorModelsim-SE MixedISE Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolPROP_Top_Level_Module_TypeVHDLPROP_DevSpeed-5PROP_DevPackagevq100PROP_DevDevicexc3s100exc3s1600exc3s1200exc3s250epq208ft256cp132PROP_ParSmartGuideFileNamevg_z80_sbc_guide.ncdPROP_UseSmartGuidePROP_SynthTopNCD files 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 !"#$%&'()*+,-./0123456789:;<=>?@ABCD0EFGH.IJK.LMN.OPQRST.UVWXYZ[\]^_`abcdefghijklmnPK
ML" inputState="Unknown" file="vg_z80_sbc_partitions.html" label="Partition Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="vg_z80_sbc_map.mrp" label="IOB Properties" />   <view program="map" type="Module_Utilization" inputState="Translated" file="vg_z80_sbc_map.mrp" label="Module Level Utilization" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="vg_z80_sbc.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="vg_z80_sbc.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="vg_z80_sbc.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view hidden="true" program="xpwr" type="MessageList" inputState="Routed" file="_xmsgs/xpwr.xmsgs" label="Power Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="vg_z80_sbc.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="vg_z80_sbc.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="vg_z80_sbc_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Details" target="Section 12 - " />    <toc-item title="Section 13: Control Set Information" target="Section 13 - " />    <toc-item title="Section 14: Utilization by Hierarchy" target="Section 14 - " />   <view program="par" type="Report" inputState="Mapped" file="vg_z80_sbc.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" type="Report" inputState="Routed" file="vg_z80_sbc.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="vg_z80_sbc.pwr" label="Power Report" >    <toc-item title="Power summary" target="Power summary" />    <toc-item title="Thermal summary" target="Thermal summary" />   <view program="bitgen" type="Report" inputState="Routed" file="vg_z80_sbc.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Synthesized" file="netgen/synthesis/vg_z80_sbc_synthesis.nlf" label="Post-Synthesis Simulation Model Report" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="vg_z80_sbc_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc_xplorer.rpt" label="Xplorer Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/vg_z80_sbc_translate.nlf" label="Post-Translate Simulation Model Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="vg_z80_sbc_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />   <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="vg_z80_sbc_preroute.twr" label="Post-Map Static Timing Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/vg_z80_sbc_map.nlf" label="Post-Map Simulation Model Report" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Mapped" file="vg_z80_sbc_map.psr" label="Physical Synthesis Report" />   <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="vg_z80_sbc_pad.txt" label="Pad Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="vg_z80_sbc.unroutes" label="Unroutes Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="vg_z80_sbc.grf" label="Guide Results Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc.dly" label="Asynchronous Delay Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc.clk_rgn" label="Clock Region Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc_par_fecn.nlf" label="Post-Place and Route Formality Netlist" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/vg_z80_sbc_timesim.nlf" label="Post-Place and Route Simulation Model Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc_sta.nlf" label="Primetime Netlist Report" />   <view hidden="true" program="ibiswriter" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc.ibs" label="IBIS Model" >    <toc-item title="Top of Report" target="Xilinx Virtex IBIS File" />    <toc-item title="Component" target="Component " />   <view hidden="true" program="pin2ucf" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc.lck" label="Back-annotate Pin Report" >    <toc-item title="Top of Report" target="pin2ucf Report File" />    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />   <view hidden="true" program="pin2ucf" type="Secondary_Report" inputState="Routed" file="vg_z80_sbc.lpc" label="Locked Pin Constraints" >    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> </body></report-views>PK

 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGH-IJK-LMN-OPQRST-UVWXYZ[\]^_`abcdefghijklmnPK
ml" label="Partition Report"  hidden="true">   <view program="map" inputState="Translated" type="IOBProperties" file="!module_name!_map.mrp" label="IOB Properties" />   <view program="map" inputState="Translated" type="Module_Utilization" file="!module_name!_map.mrp" label="Module Level Utilization" />   <view program="par" inputState="Mapped" type="ConstraintsData" file="!module_name!.par" label="Timing Constraints" />   <view program="par" inputState="Mapped" type="PinoutData" file="!module_name!.pad" label="Pinout Report" />   <view program="par" inputState="Mapped" type="ClocksData" file="!module_name!.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered"/>   <view program="ngdbuild" inputState="Synthesized" type="MessageList" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered"/>   <view program="map" inputState="Translated" type="MessageList"  file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered"/>   <view program="par" inputState="Mapped" type="MessageList"  file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered"/>   <view program="trce" inputState="Routed" type="MessageList"  file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered"/>   <view program="xpwr" inputState="Routed" type="MessageList"  file="_xmsgs/xpwr.xmsgs" label="Power Messages" hideColumns="Filtered" hidden="true"/>   <view program="bitgen" inputState="Routed" type="MessageList" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered"/>   <view program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" inputState="Current" type="MessageList"  file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered"/>  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="!module_name!.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation"           target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis"              target="   HDL Analysis   " />    <toc-item title="HDL Synthesis"             target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis"    target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis"       target="   Low Level Synthesis   " />    <toc-item title="Partition Report"          target="   Partition Report     " />    <toc-item title="Final Report"              target="   Final Report   " />   <view program="ngdbuild" inputState="Synthesized" type="Report" file="!module_name!.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status"          target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" inputState="Translated" type="Report" file="!module_name!_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors"                             target="Section 1 - " />    <toc-item title="Section 2: Warnings"                           target="Section 2 - " />    <toc-item title="Section 3: Infos"                              target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary"              target="Section 4 - " />    <toc-item title="Section 5: Removed Logic"                      target="Section 5 - " />    <toc-item title="Section 6: IOB Properties"                     target="Section 6 - " />    <toc-item title="Section 7: RPMs"                               target="Section 7 - " />    <toc-item title="Section 8: Guide Report"                       target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary"   target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary"            target="Section 10 - " />    <toc-item title="Section 11: Timing Report"                     target="Section 11 - " />    <toc-item title="Section 12: Configuration String Details"      target="Section 12 - " />    <toc-item title="Section 13: Control Set Information"           target="Section 13 - " />    <toc-item title="Section 14: Utilization by Hierarchy"          target="Section 14 - " />   <view program="par" inputState="Mapped" type="Report" file="!module_name!.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Partition Status"   target="Partition Implementation Status" />    <toc-item title="Clock Report"       target="Generating Clock Report" />    <toc-item title="Timing Results"     target="Timing Score:" />    <toc-item title="Final Summary"      target="Peak Memory Usage:" />   <view program="trce" inputState="Routed" type="Report" file="!module_name!.twr" label="Static Timing Report">    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="xpwr" inputState="Routed" type="Report" file="!module_name!.pwr" label="Power Report" hidden="true">    <toc-item title="Power summary" target="Power summary" />    <toc-item title="Thermal summary" target="Thermal summary" />   <view program="bitgen" inputState="Routed" type="Report" file="!module_name!.bgn" label="Bitgen Report">    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view program="isim" inputState="PreSynthesized" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" hidden="true"/>   <view program="netgen" inputState="Synthesized" type="Secondary_Report" file="netgen/synthesis/!module_name!_synthesis.nlf" label="Post-Synthesis Simulation Model Report" hidden="true"/>   <view program="map" inputState="Translated" type="Secondary_Report" file="!module_name!_map.map" label="Map Log File" hidden="true">    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary"     target="Design Summary" />   <view program="xplorer" inputState="Routed" type="Secondary_Report" file="!module_name!_xplorer.rpt" label="Xplorer Report" hidden="true"/>   <view program="netgen" inputState="Translated" type="Secondary_Report" file="netgen/translate/!module_name!_translate.nlf" label="Post-Translate Simulation Model Report" hidden="true"/>   <view program="netgen" inputState="Translated" type="Secondary_Report" file="!module_name!_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" hidden="true"/>   <view program="trce" inputState="Mapped" type="Secondary_Report" file="!module_name!_preroute.twr" label="Post-Map Static Timing Report"  hidden="true"/>   <view program="netgen" inputState="Mapped" type="Secondary_Report" file="netgen/map/!module_name!_map.nlf" label="Post-Map Simulation Model Report" hidden="true"/>   <view program="map" inputState="Mapped" type="Secondary_Report" file="!module_name!_map.psr" label="Physical Synthesis Report" hidden="true">   <view program="par" inputState="Mapped" type="Pad_Report" file="!module_name!_pad.txt" label="Pad Report"  hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.unroutes" label="Unroutes Report" hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.grf" label="Guide Results Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.dly" label="Asynchronous Delay Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.clk_rgn" label="Clock Region Report" hidden="true"/>   <view program="netgen" inputState="Routed" type="Secondary_Report" file="!module_name!_par_fecn.nlf" label="Post-Place and Route Formality Netlist" hidden="true">   <view program="netgen" inputState="Routed" type="Secondary_Report" file="netgen/par/!module_name!_timesim.nlf" label="Post-Place and Route Simulation Model Report" hidden="true">   <view program="netgen" inputState="Routed" type="Secondary_Report" file="!module_name!_sta.nlf" label="Primetime Netlist Report"  hidden="true">   <view program="ibiswriter" inputState="Routed" type="Secondary_Report" file="!module_name!.ibs" label="IBIS Model"  hidden="true">    <toc-item title="Top of Report" target="Xilinx Virtex IBIS File" />    <toc-item title="Component" target="Component " />   <view program="pin2ucf" inputState="Routed" type="Secondary_Report" file="!module_name!.lck" label="Back-annotate Pin Report"  hidden="true">    <toc-item title="Top of Report" target="pin2ucf Report File" />    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />   <view program="pin2ucf" inputState="Routed" type="Secondary_Report" file="!module_name!.lpc" label="Locked Pin Constraints"  hidden="true">    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> </body></report-views>PK

__REGISTRY__/PK
__REGISTRY__/Autonym/PK
__REGISTRY__/Autonym/regkeysPK
#__REGISTRY__/ExpandedNetlistEngine/PK
*__REGISTRY__/ExpandedNetlistEngine/regkeysPK
 __REGISTRY__/HierarchicalDesign/PK
*__REGISTRY__/HierarchicalDesign/HDProject/PK

s
CommandLine-Ngdbuild
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 vg_z80_sbc.ngc vg_z80_sbc.ngd
s
CommandLine-Par

s
CommandLine-Xst

s
Previous-NGD
vg_z80_sbc_prev_built.ngd
s
Previous-NGM

s
Previous-Packed-NCD

s
Previous-Routed-NCD

s
PK
'__REGISTRY__/HierarchicalDesign/regkeysPK
__REGISTRY__/ProjectNavigator/PK
10.1
s
PK
!__REGISTRY__/ProjectNavigatorGui/PK
(__REGISTRY__/ProjectNavigatorGui/regkeysPK
__REGISTRY__/STE/PK
__REGISTRY__/STE/bitgen/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -f vg_z80_sbc.ut vg_z80_sbc.ncd
s
FormatString
bitgen [-d] [-j] [-b] [-w] [-l] [-m] [-t] [-n] [-u] [-a] [--p] [-r <bitFile>] [-intstyle ise|xflow|silent] [-ise <projectrepositoryfile>] {-bd <BRAM_data_file> [tag <tagname>]} {-g <setting_value>} <infile[.ncd]> [<outfile>] [<pcffile[.pcf]>]
s
PK
__REGISTRY__/STE/map/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -p xc3s500e-fg320-4 -timing -logic_opt off -ol high -xe n -t 1 -cm area -pr b -k 4 -power off -o vg_z80_sbc_map.ncd vg_z80_sbc.ngd vg_z80_sbc.pcf
s
FormatString
map <infile[.ngd]> [-bp] [-c [<packfactor:0,100>]] [-cm <covermode>] [-detail] [-equivalent_register_removal on|off] [-global_opt off|&speed|&area|on] [-ignore_keep_hierarchy] [-intstyle ise|xflow|silent] [-ir] [-ise <iseProjectFile>] [-k 4|5|6|7|8] [-l] [-lc off|area|auto] [-logic_opt off|on] [-ntd] [-o <outfile[.ncd]>] [-ol std|med|high] [-p <partname>] [-power off|on] [-activityfile <activityfile[.vcd|.saif]>] [-pr off|i|o|b] [-r] [-register_duplication [off|on]] [-retiming off|on] [-smartguide <guide[.ncd]>] [-t <costtable:1,100>] [-timing] [-tx on|off|aggressive|limit] [-u]  [-w]  [-x]  [-xe c|n] [--ds <doodlescript>] [--hv] [--lambda <inputlambda:1,15> <outputlambda:1,4>] [--m]  [--ms <mapscript>] [--physical_synthesis off|on] [--smartsynthesis <value>] [--ts_comb <combll> <combul>] [--ts_cy <cyll> <cyul>] [--ts_load <load>] [--ts_trigger <trigger>] [--use_soft_locs] [--global_opt_script <file>] [<prffile[.pcf]>]
s
PK
__REGISTRY__/STE/ngdbuild/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 vg_z80_sbc.ngc vg_z80_sbc.ngd
s
FormatString
ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur <rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off] [-uc <ucf_file[.ucf]>] [-aul] [-bm <bmm_file[.bmm]>] [-i] [-modular initial|module|assemble] [-intstyle ise|xflow|silent] [-quiet] [-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim <pim_module_name>} [-insert_keep_hierarchy] [--forcengd] {--n <ngl_file>} {--sl <library>} [--global_opt] [--script <tcl_file>] [--incremental] [--csttrans] <design_name> [<ngd_file[.ngd]>]
s
PK
__REGISTRY__/STE/par/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -w -intstyle ise -pl high -rl high -xe n -t 1 vg_z80_sbc_map.ncd vg_z80_sbc.ncd vg_z80_sbc.pcf
s
FormatString
par [-ol std|med|high] [-pl std|med|high] [-rl std|med|high] [-xe n|c] [-t <costtable:1,100>] [-p] [-k] [-r] [-w] [-smartguide <guidefile[.ncd]>] [-n <iterations:0,100>] [-s <savebest:1,100>] [-m <nodelistfile>] [-x] [-ub] [-nopad] [-power on|off] [-activityfile <activityfile[.vcd|.saif]>] [-ntd] [-intstyle ise|xflow|silent] [-ise <projectrepositoryfile>] [--strategy use_placement|keep_placement|ignore_placement]<infile[.ncd]> <outfile> [<constraintsfile[.pcf]>]
s
PK
__REGISTRY__/STE/trce/PK
C:/Xilinx/10.1/ISE/bin/nt/unwrapped/trce.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -e 3 -s 4 -xml vg_z80_sbc vg_z80_sbc.ncd -o vg_z80_sbc.twr vg_z80_sbc.pcf -ucf vg_z80_sbc.ucf
s
FormatString
trce.exe ([-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n [<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-skew] [-a] [--p] [-s <speed>] [-o <report[.twr]>] [--m] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml <report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-intstyle ise|xflow|silent] [-ise <projectfile>] [--ucf <constraint[.ucf]>] <design[.ncd]> [<constraint[.pcf]>]) | ([-run <macro[.xtm]> [<design[.ncd]> [<constraint[.pcf]>]]] [-intstyle ise|xflow|silent] [-ise <projectfile>])
s
PK
__REGISTRY__/STE/xst/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_s3e_sk.ise -intstyle ise -ifn C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.xst -ofn C:/opencores/vg_z80_sbc/vg_s3e_sk/vg_z80_sbc.syr -finalclean 1
s
FormatString
xst [-ifn <InputFile>] [-ofn <OutputFile>] [-ise <iseProjectFile>] [--quiet] [-intstyle <Style>] [--deb <DebugLevel>] [--finalclean <Clean>] [--PcubeFlow] [--globOptFlow] [--XstNtrc]
s
PK
Co//__REGISTRY__/STE/regkeysMostRecentClient
bitgen
s
SteInfoVersion
0.0
s
PK
__REGISTRY__/SrcCtrl/PK
__REGISTRY__/SrcCtrl/regkeysPK
__REGISTRY__/XSLTProcess/PK
_xmsgs/XSLTProcess.xmsgs
s
PK
 __REGISTRY__/_ProjRepoInternal_/PK
10.1
s
ISE_VERSION_LAST_SAVED_WITH
10.1
s
LastRepoDir
C:\opencores\vg_z80_sbc\vg_s3e_sk\
s
OBJSTORE_VERSION
1.3
s
PROJECT_CREATION_TIMESTAMP
2008-12-04T16:23:56
s
REGISTRY_VERSION
1.1
s
REPOSITORY_VERSION
1.1
s
PK
__REGISTRY__/bitgen/PK
_xmsgs/bitgen.xmsgs
s
PK
__REGISTRY__/common/PK
false
s
MessageCaptureEnabled
true
s
MessageFilterFile
filter.filter
s
MessageFilteringEnabled
false
s
RunOnce
#/PnAutoRun/Scripts/RunOnce_tcl
s
PK
__REGISTRY__/cpldfit/PK
_xmsgs/cpldfit.xmsgs
s
PK
__REGISTRY__/dumpngdio/PK
_xmsgs/dumpngdio.xmsgs
s
PK
__REGISTRY__/fuse/PK
_xmsgs/fuse.xmsgs
s
PK
__REGISTRY__/hprep6/PK
_xmsgs/hprep6.xmsgs
s
PK
__REGISTRY__/idem/PK
_xmsgs/idem.xmsgs
s
PK
__REGISTRY__/map/PK
_xmsgs/map.xmsgs
s
PK
__REGISTRY__/netgen/PK
_xmsgs/netgen.xmsgs
s
PK
__REGISTRY__/ngc2edif/PK
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
_xmsgs/ngc2edif.xmsgs
s
PK
__REGISTRY__/ngcbuild/PK
_xmsgs/ngcbuild.xmsgs
s
PK
__REGISTRY__/ngdbuild/PK
_xmsgs/ngdbuild.xmsgs
s
PK
__REGISTRY__/par/PK
_xmsgs/par.xmsgs
s
PK
__REGISTRY__/runner/PK
_xmsgs/runner.xmsgs
s
PK
__REGISTRY__/taengine/PK
_xmsgs/taengine.xmsgs
s
PK
__REGISTRY__/trce/PK
,,__REGISTRY__/trce/regkeysClientMessageOutputFile
_xmsgs/trce.xmsgs
s
PK
__REGISTRY__/tsim/PK
_xmsgs/tsim.xmsgs
s
PK
__REGISTRY__/vhpcomp/PK
_xmsgs/vhpcomp.xmsgs
s
PK
__REGISTRY__/vlogcomp/PK
_xmsgs/vlogcomp.xmsgs
s
PK
__REGISTRY__/xpwr/PK
_xmsgs/xpwr.xmsgs
s
PK
__REGISTRY__/xreport/PK
__REGISTRY__/xreport/regkeysPK
__REGISTRY__/xst/PK
_xmsgs/xst.xmsgs
s
PK
1.1
REGISTRY_VERSION
1.1
OBJSTORE_VERSION
1.3
ISE_VERSION_CREATED_WITH
10.1
ISE_VERSION_LAST_SAVED_WITH
10.1

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