Subversion Repositories vg_z80_sbc

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments

NET "CLK"  LOC = "C9" | IOSTANDARD = LVCMOS33 ; 
NET "CLK" PERIOD = 20 HIGH 50%;   # 50 MHZ 
#NET "reset"   LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "RST"  LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; 
#NET "BTN_NORTH"  LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; 

# RS-232 UART, J10 - DTE Male DB9
NET "CONS_UART_TXD"  LOC = "M13" | IOSTANDARD = LVTTL  | SLEW = SLOW  | DRIVE = 8 ;
NET "CONS_UART_RXD"  LOC = "U8" | IOSTANDARD = LVTTL | PULLUP ;

# RS-232 UART, J9 - DCE Female DB9
NET "AUX_UART_TXD"  LOC = "M14" | IOSTANDARD = LVTTL  | SLEW = SLOW  | DRIVE = 8 ;
NET "AUX_UART_RXD"  LOC = "R7" | IOSTANDARD = LVTTL | PULLUP ;

# Intel StrataFLASH
NET "FLASH_A<0>"  LOC = "H17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<1>"  LOC = "J13" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<2>"  LOC = "J12" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<3>"  LOC = "J14" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<4>"  LOC = "J15" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<5>"  LOC = "J16" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<6>"  LOC = "J17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<7>"  LOC = "K14" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<8>"  LOC = "K15" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<9>"  LOC = "K12" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;

NET "FLASH_D<0>"  LOC = "N10" | IOSTANDARD = LVCMOS33 | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<1>"  LOC = "P10" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<2>"  LOC = "R10" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<3>"  LOC = "V9" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<4>"  LOC = "U9" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<5>"  LOC = "R9" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<6>"  LOC = "M9" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_D<7>"  LOC = "N9" | IOSTANDARD = LVCMOS33  | KEEPER | SLEW = SLOW  | DRIVE = 4;

NET "FLASH_CE"  LOC = "D16" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_OE"  LOC = "C18" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_WE"  LOC = "D17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;

NET "FLASH_BYTE"  LOC = "C17" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
NET "FLASH_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;
#NET "FLASH_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33  | SLEW = SLOW  | DRIVE = 4;

# VGA Port
NET "hsync"  LOC = "F15" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8;
NET "vsync"  LOC = "F14" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8;
NET "R"  LOC = "H14" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8;
NET "G"  LOC = "H15" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8;
NET "B"  LOC = "G15" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8;

# PS/2 Port
NET "PS2_KBD_CLK"  LOC = "G14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "PS2_KBD_DAT"  LOC = "G13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;

## DDR SDRAM
# ==== Ignore timing over async-fifos ==== 
#NET "CLK_IBUFG"               TNM="SYS_CLK"; 
#NET "*/clkgen/write_clk_u"    TNM="WRITE_CLK"; 
#NET "*/clkgen/write_clk90_u"  TNM="WRITE_CLK"; 
#NET "*/ctrl0/write_clk"       TNM="WRITE_CLK"; 
#NET "*/ctrl0/write_clk90"     TNM="WRITE_CLK"; 
#NET "*/ctrl0/clkgen/read_clk_u" TNM="READ_CLK"; 
#NET "*/ctrl0/read_clk"        TNM="READ_CLK"; 
#NET "*/clkgen/read_clk_u"     TNM="READ_CLK"; 
#NET "*/clkgen/read_clk180_u"  TNM="DDR_CLK"; 

##----- commented out to remove wb_ddr 
#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG; 
# 
#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG; 
#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG; 
#  
#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG; 
#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG; 
# 
## ==== Place both DCMs at the bottom ==== 
#INST "*/clkgen/dcm_fx"    LOC="DCM_X0Y1"; 
#INST "*/clkgen/dcm_phase" LOC="DCM_X1Y1"; 
#
#NET "SD_CK_P"    LOC = "J5" | IOSTANDARD = SSTL2_I ;
#NET "SD_CK_N"    LOC = "J4" | IOSTANDARD = SSTL2_I ;
#
#NET "SD_A<12>"  LOC = "P2" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<11>"  LOC = "N5" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<10>"  LOC = "T2" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<9>"   LOC = "N4" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<8>"   LOC = "H2" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<7>"   LOC = "H1" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<6>"   LOC = "H3" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<5>"   LOC = "H4" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<4>"   LOC = "F4" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<3>"   LOC = "P1" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<2>"   LOC = "R2" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<1>"   LOC = "R3" | IOSTANDARD = SSTL2_I ;
#NET "SD_A<0>"   LOC = "T1" | IOSTANDARD = SSTL2_I ;
#
#NET "SD_BA<0>"   LOC = "K5" | IOSTANDARD = SSTL2_I ;
#NET "SD_BA<1>"   LOC = "K6" | IOSTANDARD = SSTL2_I ;
#
#NET "SD_DQ<0>"   LOC = "L2" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<1>"   LOC = "L1" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<2>"   LOC = "L3" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<3>"   LOC = "L4" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<4>"   LOC = "M3" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<5>"   LOC = "M4" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<6>"   LOC = "M5" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<7>"   LOC = "M6" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<8>"   LOC = "E2" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<9>"   LOC = "E1" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<10>"  LOC = "F1" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<11>"  LOC = "F2" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<12>"  LOC = "G6" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<13>"  LOC = "G5" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<14>"  LOC = "H6" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQ<15>"  LOC = "H5" | IOSTANDARD = SSTL2_I ;
#
#NET "SD_DM<0>"   LOC = "J2" | IOSTANDARD = SSTL2_I ;
#NET "SD_DM<1>"   LOC = "J1" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQS<0>"  LOC = "L6" | IOSTANDARD = SSTL2_I ;
#NET "SD_DQS<1>"  LOC = "G3" | IOSTANDARD = SSTL2_I ;
#NET "SD_CS"      LOC = "K4" | IOSTANDARD = SSTL2_I ;
#NET "SD_CKE"     LOC = "K3" | IOSTANDARD = SSTL2_I ;
#NET "SD_RAS"     LOC = "C1" | IOSTANDARD = SSTL2_I ;
#NET "SD_CAS"     LOC = "C2" | IOSTANDARD = SSTL2_I ;
#NET "SD_WE"      LOC = "D1" | IOSTANDARD = SSTL2_I ;
#
## Path to allow connection to top DCM connection
##NET "SD_CK_FB"   LOC = "B9" | IOSTANDARD = LVCMOS33 ;
#
## ==== rotary encoder ====
#NET "rot<0>"  LOC = "K18" | IOSTANDARD = LVTTL | PULLUP   ;
#NET "rot<1>"  LOC = "G18" | IOSTANDARD = LVTTL | PULLUP   ;
#NET "rot<2>"  LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
##----- end commented out to remove wb_ddr

# SD-SPI Interface
NET "SD_SPI_CLK"  LOC = "D7" | IOSTANDARD = LVTTL ;
NET "SD_SPI_MISO" LOC = "C7" | IOSTANDARD = LVTTL | PULLUP   ;
NET "SD_SPI_MOSI" LOC = "F8" | IOSTANDARD = LVTTL;
NET "SD_SPI_CS_N" LOC = "E8" | IOSTANDARD = LVTTL;

# Discrete LEDs
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

# Switches (Slide Switches)
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

# LCD Interface
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# The LCD four-bit data interface is shared with the StrataFlash.
NET "LCD_D<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_D<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_D<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_D<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

# Prohibit VREF Pins
CONFIG PROHIBIT = D2 ;
CONFIG PROHIBIT = G4 ;
CONFIG PROHIBIT = J6 ;
CONFIG PROHIBIT = L5 ;
CONFIG PROHIBIT = R4 ;