Subversion Repositories vga_lcd

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#
# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
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# ==============================================
# Setup Design Parameters

set design_files {ud_cnt ro_cnt vga_fifo_dc vga_fifo vga_colproc vga_vtim vga_pgen vga_wb_master vga_tgen vga_wb_slave vga_csm_pb vga_top vga_vga_and_clut}


set design_name vga_vga_and_clut
set active_design vga_vga_and_clut
 
# Next Statement defines all clocks and resets in the design
set special_net {rst clk_i pclk}
 
set hdl_src_dir ../../rtl/verilog/