Subversion Repositories via6522

# via6522x12
(C) 2022 Robert Finch

## Overview
The via6522x12 is a versatile interface adapter 12-bit peripheral core that is register compatible with a 6522.
The core may also be configured for eight bit operation.
## Features
* 2 12-bit ports
* 3 24-bit timers
* 1 12-bit shift register
## Registers
|Reg |Bits|Moniker| Description            | Comment        |
|----|----|-------|------------------------|----------------|
| 00 | 12 |  PB   | Port B I/O             |                |
| 01 | 12 |  PA   | Port A I/O             | handshaking    |
| 02 | 12 | PBDDR | Port B data direction  |                |
| 03 | 12 | PADDR | Port A data direction  |                |
| 04 | 12 | T1CL  | Time 1 count low       |                |
| 05 | 12 | T1CH  | Time 1 count high      |                |
| 06 | 12 | T1LL  | Time 1 latch low       |                |
| 07 | 12 | T1LH  | Time 1 latch high      |                |
| 08 | 12 | T2CL  | Time 2 count low       |                |
| 09 | 12 | T2CH  | Time 2 count high      |                |
| 10 | 12 |  SR   | Shift register         |                |
| 11 | 12 | ACR   | Auxillary control reg  |                |
| 12 | 12 | PCR   | Peripheral control reg |                |
| 13 | 12 | IFR   | Interrupt flag reg     |                |
| 14 | 12 | IER   | Interrupt enable reg   |                |
| 15 | 12 |  PA   | Port A I/O             | no-handshaking |
| 16 | 12 | T3CL  | Timer 3 count low      |                |
| 17 | 12 | T3CH  | Timer 3 count high     |                |
| 18 | 12 | T3LL  | Timer 3 latch low      |                |
| 19 | 12 | T3LH  | Timer 3 latch high     |                |
| 20 | 12 | T3CMPL| Timer 3 compare low    |                |
| 21 | 12 | T3CMPH| Timer 3 compare high   |                |

### PB (Reg 00)
Operates in the same manner as the 6522 port B but is 12-bits wide rather than 8-bits. If port B input latching is enabled, then input data on port B is latched by an active transition of the selected handshaking signal. Otherwise input data is reflected directly by reading the port register.
### PA (Reg 01)
Operates in the same manner as the 6522 port A but is 12-bits wide rather than 8-bits. If port A input latching is enabled, then input data on port A is latched by an active transition of the selected handshaking signal. Otherwise input data is reflected directly by reading the port register.
### PBDDR (Reg 02)
### PADDR (Reg 03)
### T1CL (Reg 04)
Similar function to the reg 4 of the 6522. Provides read access to the low order 12-bits of timer 1. Acts as a latch for the low 12-bits of the value to be loaded into the timer. 
### T1CH (Reg 05)
Similar in function to register 5 of the 6522. When the timer is in 24-bit mode writing this register transfers bit 0 to 11 of the timer 1 latch to bits 0 to 11 of the timer and transfers input data bits 0 to 11 to counter bits 12 to 23 of the timer.
### T1LL (Reg 06)
Similar in function to register 6 of the 6522. Provides access to the timer 1 low order latches.
### T1LH (Reg 07)
Similar in function to register 7 of the 6522. Provides access to the timer 1 high order latches.
### T2CL (Reg 08)
Similar in function to register 8 of the 6522. Provides access to timer 2 low order latch / count.
### T2CH (Reg 09)
Similar in function to register 9 of the 6522. Provides access to timer 2 high order latch / count.
### SR (Reg 10)
Similar in function to register 10 of the 6522. The shift register is 12-bits wide.
### ACR (Reg 11)
| Bits | Function                             |
|------|--------------------------------------|
|  0   | port A input latch enable            |
|  1   | port B input latch enable            |
| 2-4  | shift register mode                  |
|  5   | timer #2 mode                        |
| 6-7  | timer #1 mode                        |
|  8   | timer #3 mode                        |
### PCR (Reg 12)
| Bits | Function                             |
|------|--------------------------------------|
|  0   | CA1 mode                             |
| 1-3  | CA2 mode                             |
|  4   | CB1 mode                             |
| 5-7  | CB2 mode                             |
### IFR (Reg 13)
| Bits | Function                             |
|------|--------------------------------------|
|  0   | CA2 active transition                |
|  1   | CA1 active transition                |
|  2   | shift register                       |
|  3   | CB2 active transition                |
|  4   | CB1 active transition                |
|  5   | Timer #1 underflow                   |
|  6   | Timer #2 underflow                   |
|  7   | Timer #3 compare                     |
| 8-10 | reserved                             |
|  11  | Set if any interrupt is present      |
### IER (Reg 14)
| Bits | Function                             |
|------|--------------------------------------|
|  0   | CA2 active transition                |
|  1   | CA1 active transition                |
|  2   | shift register                       |
|  3   | CB2 active transition                |
|  4   | CB1 active transition                |
|  5   | Timer #1 underflow                   |
|  6   | Timer #2 underflow                   |
|  7   | Set if any interrupt is present      |
|  8   | Timer #3 compare                     |
| 9-10 | reserved                             |
### PA (Reg 15)
This is an alias to access port A except no handshaking is present.
### T3CL (Reg 16)
Provides read access to the low order 12-bits of timer 3. Acts as a latch for the low 12-bits of the value to be loaded into the timer. 
### T3CH (Reg 17)
Writing this register transfers bit 0 to 11 of the timer 3 latch to bits 0 to 11 of the timer and transfers input data bits 0 to 11 to counter bits 12 to 23 of the timer.
### T3LL (Reg 18)
Provides access to the timer 1 low order latches.
### T3LH (Reg 19)
Provides access to the timer 3 high order latches.
### T3CMPL (Reg 20)
Contains the low order 12 bits of a comparison value that will cause an interrupt flag to be set if timer #3 exceeds this value.
### T3CMPH (Reg 21)
Contains the high order 12 bits of the comparison value.

## Key Differences from a 6522
The reset input (rst_i) is active high.
The IRQ output (irq_o) is not open collector and is active high.
There is only a single active high circuit select (cs_i).

## Software Examples
The via6522x12 is being used for timing and gpio in a 12-bit 6809 test system.