URL
https://opencores.org/ocsvn/video_stream_scaler/video_stream_scaler/trunk
Subversion Repositories video_stream_scaler
[/] [video_stream_scaler/] [trunk/] [sim/] [rtl_sim/] [work/] [ram@dual@port/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity ramDualPort is generic( DATA_WIDTH : integer := 8; ADDRESS_WIDTH : integer := 8 ); port( dataA : in vl_logic_vector; dataB : in vl_logic_vector; addrA : in vl_logic_vector; addrB : in vl_logic_vector; weA : in vl_logic; weB : in vl_logic; clk : in vl_logic; qA : out vl_logic_vector; qB : out vl_logic_vector ); end ramDualPort;