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https://opencores.org/ocsvn/virtual_rs232_terminal_with_lvds_lcd/virtual_rs232_terminal_with_lvds_lcd/trunk
Subversion Repositories virtual_rs232_terminal_with_lvds_lcd
[/] [virtual_rs232_terminal_with_lvds_lcd/] [trunk/] [rtl/] [ipcore_dir/] [LogoROM.xise] - Rev 2
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="LogoROM.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="LogoROM.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
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<file xil_pn:name="LogoROM.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|LogoROM|LogoROM_a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/LogoROM" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ftg256" xil_pn:valueState="default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="LogoROM" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan3a" xil_pn:valueState="default"/>
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