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Subversion Repositories vspi
[/] [vspi/] [trunk/] [projnav/] [xps/] [system.make] - Rev 14
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################################################################## Makefile generated by Xilinx Platform Studio# Project:C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.xmp## WARNING : This file will be re-generated every time a command# to run a make target is invoked. So, any changes made to this# file manually, will be lost when make is invoked next.################################################################## Name of the Microprocessor system# The hardware specification of the system is in file :# C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.mhsinclude system_incl.make################################################################## PHONY TARGETS#################################################################.PHONY: dummy.PHONY: netlistclean.PHONY: bitsclean.PHONY: simclean.PHONY: exporttosdk################################################################## EXTERNAL TARGETS#################################################################all:@echo "Makefile to build a Microprocessor system :"@echo "Run make with any of the following targets"@echo " "@echo " netlist : Generates the netlist for the given MHS "@echo " bits : Runs Implementation tools to generate the bitstream"@echo " exporttosdk: Export files to SDK"@echo " "@echo " init_bram: Initializes bitstream with BRAM data"@echo " ace : Generate ace file from bitstream and elf"@echo " download : Downloads the bitstream onto the board"@echo " "@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"@echo " simmodel : Generates HDL simulation models for chosen simulation mode"@echo " "@echo " netlistclean: Deletes netlist"@echo " bitsclean: Deletes bit, ncd, bmm files"@echo " hwclean : Deletes implementation dir"@echo " simclean : Deletes simulation dir"@echo " clean : Deletes all generated files/directories"@echo " "bits: $(SYSTEM_BIT)ace: $(SYSTEM_ACE)exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)netlist: $(POSTSYN_NETLIST)download: $(DOWNLOAD_BIT) dummy@echo "*********************************************"@echo "Downloading Bitstream onto the target board"@echo "*********************************************"impact -batch etc/download.cmdinit_bram: $(DOWNLOAD_BIT)sim: $(DEFAULT_SIM_SCRIPT)cd simulation/behavioral & \system_fuse.cmdcd simulation/behavioral & \start /B $(SIM_CMD) -gui -tclbatch system_setup.tclsimmodel: $(DEFAULT_SIM_SCRIPT)behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)structural_model: $(STRUCTURAL_SIM_SCRIPT)clean: hwclean simcleanrm -f _impact.cmdhwclean: netlistclean bitscleanrm -rf implementation synthesis xst hdlrm -rf xst.srp $(SYSTEM).srprm -f __xps/ise/_xmsgs/bitinit.xmsgsnetlistclean:rm -f $(POSTSYN_NETLIST)rm -f platgen.logrm -f __xps/ise/_xmsgs/platgen.xmsgsrm -f $(BMM_FILE)bitsclean:rm -f $(SYSTEM_BIT)rm -f implementation/$(SYSTEM).ncdrm -f implementation/$(SYSTEM)_bd.bmmrm -f implementation/$(SYSTEM)_map.ncdrm -f implementation/download.bitrm -f __xps/$(SYSTEM)_routedsimclean:rm -rf simulation/behavioralrm -f simgen.logrm -f __xps/ise/_xmsgs/simgen.xmsgs################################################################## BOOTLOOP ELF FILES#################################################################$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)"cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)################################################################## HARDWARE IMPLEMENTATION FLOW#################################################################$(BMM_FILE) \$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \$(CORE_STATE_DEVELOPMENT_FILES)@echo "****************************************************"@echo "Creating system netlist for hardware specification.."@echo "****************************************************"platgen $(PLATGEN_OPTIONS) $(MHSFILE)$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)@echo "Running synthesis..."cd synthesis & synthesis.cmd__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)@echo "*********************************************"@echo "Running Xilinx Implementation tools.."@echo "*********************************************"@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf@cp -f etc/fast_runtime.opt implementation/xflow.optxflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngctouch __xps/$(SYSTEM)_routed$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par@echo "*********************************************"@echo "Running Bitgen.."@echo "*********************************************"@cp -f $(BITGEN_UT_FILE) implementation/bitgen.utcd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd ..$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt@cp -f implementation/$(SYSTEM)_bd.bmm .@echo "*********************************************"@echo "Initializing BRAM contents of the bitstream"@echo "*********************************************"bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)@rm -f $(SYSTEM)_bd.bmm$(SYSTEM_ACE):@echo "In order to generate ace file, you must have:-"@echo "- exactly one processor."@echo "- opb_mdm, if using microblaze."################################################################## EXPORT_TO_SDK FLOW#################################################################$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.optIF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)"psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)@rm -rf $(SYSTEM_HW_HANDOFF_BIT)@cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm@rm -rf $(SYSTEM_HW_HANDOFF_BMM)@cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)################################################################## SIMULATION FLOW################################################################################### BEHAVIORAL SIMULATION ##################$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \$(BRAMINIT_ELF_SIM_FILES)@echo "*********************************************"@echo "Creating behavioral simulation models..."@echo "*********************************************"simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)################## STRUCTURAL SIMULATION ##################$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \$(BRAMINIT_ELF_SIM_FILES)@echo "*********************************************"@echo "Creating structural simulation models..."@echo "*********************************************"simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)################## TIMING SIMULATION ##################implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \$(BRAMINIT_ELF_SIM_FILES)@echo "*********************************************"@echo "Creating timing simulation models..."@echo "*********************************************"simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)dummy:@echo ""
