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https://opencores.org/ocsvn/vtach/vtach/trunk
Subversion Repositories vtach
[/] [vtach/] [trunk/] [top.pcf] - Rev 2
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//! **************************************************************************
// Written by: Map O.61xd on Sat May 25 07:43:36 2013
//! **************************************************************************
SCHEMATIC START;
PROHIBIT = SITE "C3";
PROHIBIT = SITE "D2";
PROHIBIT = SITE "D1";
PROHIBIT = SITE "E2";
PROHIBIT = SITE "E1";
PROHIBIT = SITE "F5";
PROHIBIT = SITE "G2";
PROHIBIT = SITE "G1";
PROHIBIT = SITE "J1";
PROHIBIT = SITE "K1";
PROHIBIT = SITE "K2";
PROHIBIT = SITE "M1";
PROHIBIT = SITE "M2";
PROHIBIT = SITE "N1";
PROHIBIT = SITE "N2";
PROHIBIT = SITE "P2";
PROHIBIT = SITE "M16";
PROHIBIT = SITE "M15";
PROHIBIT = SITE "T14";
PROHIBIT = SITE "P5";
PROHIBIT = SITE "N5";
PROHIBIT = SITE "R9";
PROHIBIT = SITE "T10";
PROHIBIT = SITE "N10";
PROHIBIT = SITE "R11";
PROHIBIT = SITE "T12";
PROHIBIT = SITE "R12";
PROHIBIT = SITE "R4";
COMP "ds0" LOCATE = SITE "D14" LEVEL 1;
COMP "ds1" LOCATE = SITE "G14" LEVEL 1;
COMP "ds2" LOCATE = SITE "F14" LEVEL 1;
COMP "ds3" LOCATE = SITE "E13" LEVEL 1;
COMP "pb0" LOCATE = SITE "M13" LEVEL 1;
COMP "pb1" LOCATE = SITE "M14" LEVEL 1;
COMP "pb2" LOCATE = SITE "L13" LEVEL 1;
COMP "clk" LOCATE = SITE "T9" LEVEL 1;
COMP "segA" LOCATE = SITE "E14" LEVEL 1;
COMP "segB" LOCATE = SITE "G13" LEVEL 1;
COMP "segC" LOCATE = SITE "N15" LEVEL 1;
COMP "segD" LOCATE = SITE "P15" LEVEL 1;
COMP "segE" LOCATE = SITE "R16" LEVEL 1;
COMP "segF" LOCATE = SITE "F13" LEVEL 1;
COMP "segG" LOCATE = SITE "N16" LEVEL 1;
COMP "sw<0>" LOCATE = SITE "F12" LEVEL 1;
COMP "sw<1>" LOCATE = SITE "G12" LEVEL 1;
COMP "sw<2>" LOCATE = SITE "H14" LEVEL 1;
COMP "sw<3>" LOCATE = SITE "H13" LEVEL 1;
COMP "sw<4>" LOCATE = SITE "J14" LEVEL 1;
COMP "sw<5>" LOCATE = SITE "J13" LEVEL 1;
COMP "sw<6>" LOCATE = SITE "K14" LEVEL 1;
COMP "sw<7>" LOCATE = SITE "K13" LEVEL 1;
COMP "led<0>" LOCATE = SITE "K12" LEVEL 1;
COMP "led<1>" LOCATE = SITE "P14" LEVEL 1;
COMP "led<2>" LOCATE = SITE "L12" LEVEL 1;
COMP "led<3>" LOCATE = SITE "N14" LEVEL 1;
COMP "led<4>" LOCATE = SITE "P13" LEVEL 1;
COMP "led<5>" LOCATE = SITE "N12" LEVEL 1;
COMP "led<6>" LOCATE = SITE "P12" LEVEL 1;
COMP "led<7>" LOCATE = SITE "P11" LEVEL 1;
COMP "extreset" LOCATE = SITE "L14" LEVEL 1;
PIN
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A_pins<10>
= BEL
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A"
PINNAME CLKA;
PIN
mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B_pins<10>
= BEL
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B"
PINNAME CLKB;
TIMEGRP clockdll_CLKFX_BUF = BEL "clkdiv" PIN
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A_pins<10>"
PIN
"mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B_pins<10>"
BEL "clockdll/CLKFX_BUFG_INST.GCLKMUX" BEL "clockdll/CLKFX_BUFG_INST";
PIN clockdll/DCM_INST_pins<3> = BEL "clockdll/DCM_INST" PINNAME CLKIN;
TIMEGRP clk = PIN "clockdll/DCM_INST_pins<3>";
TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;
TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH
50%;
SCHEMATIC END;