Subversion Repositories vtach

Release 13.2 - xst O.61xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> 
Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc3s1000-4-ft256

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : Yes

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : False
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "digitadd.v" in library work
Compiling verilog file "usum.v" in library work
Module <digitadd> compiled
Compiling verilog file "bcdincr.v" in library work
Module <usum> compiled
Compiling verilog file "display.v" in library work
Module <bcdincr> compiled
Compiling verilog file "bcdneg.v" in library work
Module <DisplayHex> compiled
Module <bcdneg17> compiled
Compiling verilog file "ipcore_dir/mainmem.v" in library work
Module <bcdneg13> compiled
Compiling verilog file "io_output.v" in library work
Module <mainmem> compiled
Compiling verilog file "io_input.v" in library work
Module <io_output> compiled
Compiling verilog file "debounce.v" in library work
Module <io_input> compiled
Compiling verilog file "bcdadd.v" in library work
Module <debounce> compiled
Compiling verilog file "memory.v" in library work
Module <bcdadd> compiled
Compiling verilog file "mainclock.v" in library work
Module <memory> compiled
Compiling verilog file "alu.v" in library work
Module <mainclock> compiled
Compiling verilog file "vtach.v" in library work
Module <alu> compiled
Module <top> compiled
No errors in compilation
Analysis of file <"top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <top> in library <work>.

Analyzing hierarchy for module <memory> in library <work>.

Analyzing hierarchy for module <bcdincr> in library <work>.

Analyzing hierarchy for module <alu> in library <work>.

Analyzing hierarchy for module <mainclock> in library <work>.

Analyzing hierarchy for module <usum> in library <work>.

Analyzing hierarchy for module <io_input> in library <work>.

Analyzing hierarchy for module <io_output> in library <work>.

Analyzing hierarchy for module <debounce> in library <work> with parameters.
        inittimer = "0011000011010100000"
        initval = "00000000000000000000000000000000"
        timerwidth = "00000000000000000000000000010011"

Analyzing hierarchy for module <bcdadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <DisplayHex> in library <work> with parameters.
        clkfreq = "00000000000000000000000000010000"
        ctrbits = "00000000000000000000000000011000"
        dispfreq = "00000000000000000000000001100100"
        uplimit = "00000000000000001001110001000000"

Analyzing hierarchy for module <bcdneg17> in library <work>.

Analyzing hierarchy for module <bcdneg13> in library <work>.

Analyzing hierarchy for module <usum> in library <work>.

Analyzing hierarchy for module <bcdincr> in library <work>.

Analyzing hierarchy for module <bcdincr> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <usum> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.

Analyzing hierarchy for module <digitadd> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top>.
Module <top> is correct for synthesis.
 
Analyzing module <memory> in library <work>.
WARNING:Xst:2211 - "ipcore_dir/mainmem.v" line 18: Instantiating black box module <mainmem>.
Module <memory> is correct for synthesis.
 
Analyzing module <bcdincr> in library <work>.
Module <bcdincr> is correct for synthesis.
 
Analyzing module <usum> in library <work>.
Module <usum> is correct for synthesis.
 
Analyzing module <digitadd> in library <work>.
Module <digitadd> is correct for synthesis.
 
Analyzing module <alu> in library <work>.
Module <alu> is correct for synthesis.
 
Analyzing module <io_input> in library <work>.
Module <io_input> is correct for synthesis.
 
Analyzing module <io_output> in library <work>.
WARNING:Xst:1464 - "io_output.v" line 14: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
WARNING:Xst:864 - "io_output.v" line 14: Comparisons to 'X' or 'Z' are treated as always false.
Module <io_output> is correct for synthesis.
 
Analyzing module <DisplayHex> in library <work>.
        clkfreq = 32'sb00000000000000000000000000010000
        ctrbits = 32'sb00000000000000000000000000011000
        dispfreq = 32'sb00000000000000000000000001100100
        uplimit = 32'sb00000000000000001001110001000000
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <debounce> in library <work>.
        inittimer = 19'b0011000011010100000
        initval = 32'sb00000000000000000000000000000000
        timerwidth = 32'sb00000000000000000000000000010011
Module <debounce> is correct for synthesis.
 
Analyzing module <bcdadd> in library <work>.
Module <bcdadd> is correct for synthesis.
 
Analyzing module <bcdneg17> in library <work>.
Module <bcdneg17> is correct for synthesis.
 
Analyzing module <bcdneg13> in library <work>.
Module <bcdneg13> is correct for synthesis.
 
Analyzing module <mainclock> in library <work>.
Module <mainclock> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <mainclock>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <mainclock>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <CLKIN_IBUFG_INST> in unit <mainclock>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <mainclock>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLKFX_DIVIDE =  25" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLKFX_MULTIPLY =  16" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "SIM_MODE =  SAFE" for instance <DCM_INST> in unit <mainclock>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <mainclock>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <digitadd>.
    Related source file is "digitadd.v".
    Found 5-bit adder for signal <temp>.
    Found 5-bit adder for signal <temp$addsub0000> created at line 6.
    Summary:
        inferred   2 Adder/Subtractor(s).
Unit <digitadd> synthesized.


Synthesizing Unit <io_input>.
    Related source file is "io_input.v".
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 13-bit tristate buffer for signal <value>.
    Found 13-bit register for signal <v>.
    Summary:
        inferred  13 D-type flip-flop(s).
        inferred  13 Tristate(s).
Unit <io_input> synthesized.


Synthesizing Unit <debounce>.
    Related source file is "debounce.v".
    Found 1-bit register for signal <btnout>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   5 D-type flip-flop(s).
Unit <debounce> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "display.v".
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 4-bit 4-to-1 multiplexer for signal <rNybble>.
    Summary:
        inferred   2 Counter(s).
        inferred  11 D-type flip-flop(s).
        inferred   4 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <memory>.
    Related source file is "memory.v".
    Found 13-bit tristate buffer for signal <dbus>.
    Found 7-bit adder for signal <binaddress>.
    Found 7-bit adder for signal <binaddress$addsub0000> created at line 16.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  13 Tristate(s).
Unit <memory> synthesized.


Synthesizing Unit <mainclock>.
    Related source file is "mainclock.v".
Unit <mainclock> synthesized.


Synthesizing Unit <usum>.
    Related source file is "usum.v".
    Found 1-bit adder for signal <z<16>>.
    Found 1-bit adder for signal <z_16$addsub0000> created at line 10.
    Summary:
        inferred   2 Adder/Subtractor(s).
Unit <usum> synthesized.


Synthesizing Unit <io_output>.
    Related source file is "io_output.v".
    Found 13-bit register for signal <val>.
    Summary:
        inferred  13 D-type flip-flop(s).
Unit <io_output> synthesized.


Synthesizing Unit <bcdincr>.
    Related source file is "bcdincr.v".
Unit <bcdincr> synthesized.


Synthesizing Unit <bcdneg17>.
    Related source file is "bcdneg.v".
    Found 4-bit adder for signal <$sub0000> created at line 13.
    Found 4-bit adder for signal <$sub0001> created at line 13.
    Found 4-bit adder for signal <$sub0002> created at line 13.
    Found 4-bit adder for signal <$sub0003> created at line 13.
    Summary:
        inferred   4 Adder/Subtractor(s).
Unit <bcdneg17> synthesized.


Synthesizing Unit <bcdneg13>.
    Related source file is "bcdneg.v".
    Found 4-bit adder for signal <$sub0000> created at line 21.
    Found 4-bit adder for signal <$sub0001> created at line 21.
    Found 4-bit adder for signal <$sub0002> created at line 21.
    Summary:
        inferred   3 Adder/Subtractor(s).
Unit <bcdneg13> synthesized.


Synthesizing Unit <bcdadd>.
    Related source file is "bcdadd.v".
Unit <bcdadd> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 13-bit tristate buffer for signal <dbus>.
    Found 1-bit register for signal <halt>.
    Found 1-bit register for signal <memwrite>.
    Found 17-bit register for signal <acc>.
    Found 1-bit register for signal <isel>.
    Found 1-bit register for signal <osel>.
    Summary:
        inferred  21 D-type flip-flop(s).
        inferred  26 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <top>.
    Related source file is "vtach.v".
    Found 1-bit register for signal <addsource>.
    Found 8-bit register for signal <bug>.
    Found 1-bit register for signal <clkdiv>.
    Found 4-bit register for signal <clkphase>.
    Found 12-bit register for signal <ir>.
    Found 1-bit register for signal <memoe>.
    Found 1-bit register for signal <reset>.
    Summary:
        inferred  28 D-type flip-flop(s).
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 63
 1-bit adder                                           : 10
 4-bit adder                                           : 11
 5-bit adder                                           : 40
 7-bit adder                                           : 2
# Counters                                             : 5
 19-bit down counter                                   : 3
 2-bit down counter                                    : 1
 24-bit up counter                                     : 1
# Registers                                            : 40
 1-bit register                                        : 34
 12-bit register                                       : 1
 13-bit register                                       : 2
 17-bit register                                       : 1
 4-bit register                                        : 1
 8-bit register                                        : 1
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-4 decoder                                        : 1
# Tristates                                            : 4
 13-bit tristate buffer                                : 4
# Xors                                                 : 3
 1-bit xor2                                            : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <ipcore_dir/mainmem.ngc>.
Loading core <mainmem> for timing and area information for instance <ram>.
WARNING:Xst:1290 - Hierarchical block <add3> is unconnected in block <inc>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <add4> is unconnected in block <inc>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <add4> is unconnected in block <inc>.
   It will be removed from the design.
INFO:Xst:2261 - The FF/Latch <v_8> in Unit <in> is equivalent to the following 4 FFs/Latches, which will be removed : <v_9> <v_10> <v_11> <v_12> 
WARNING:Xst:1710 - FF/Latch <v_8> (without init value) has a constant value of 0 in block <in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2404 -  FFs/Latches <v<12:8>> (without init value) have a constant value of 0 in block <io_input>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 38
 1-bit adder carry in                                  : 5
 4-bit adder                                           : 11
 5-bit adder carry in                                  : 20
 7-bit adder                                           : 2
# Counters                                             : 5
 19-bit down counter                                   : 3
 2-bit down counter                                    : 1
 24-bit up counter                                     : 1
# Registers                                            : 96
 Flip-Flops                                            : 96
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-4 decoder                                        : 1
# Xors                                                 : 3
 1-bit xor2                                            : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1901 - Instance U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram in unit U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram of type RAMB16_S36_S36 has been replaced by RAMB16
WARNING:Xst:2040 - Unit alu: 13 multi-source signals are replaced by logic (pull-up yes): dbus<0>, dbus<10>, dbus<11>, dbus<12>, dbus<1>, dbus<2>, dbus<3>, dbus<4>, dbus<5>, dbus<6>, dbus<7>, dbus<8>, dbus<9>.
WARNING:Xst:2042 - Unit memory: 13 internal tristates are replaced by logic (pull-up yes): dbus<0>, dbus<10>, dbus<11>, dbus<12>, dbus<1>, dbus<2>, dbus<3>, dbus<4>, dbus<5>, dbus<6>, dbus<7>, dbus<8>, dbus<9>.
WARNING:Xst:2042 - Unit io_input: 13 internal tristates are replaced by logic (pull-up yes): value<0>, value<10>, value<11>, value<12>, value<1>, value<2>, value<3>, value<4>, value<5>, value<6>, value<7>, value<8>, value<9>.

Optimizing unit <top> ...

Optimizing unit <digitadd> ...

Optimizing unit <debounce> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <io_output> ...

Optimizing unit <bcdneg17> ...

Optimizing unit <bcdneg13> ...

Optimizing unit <bcdadd> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 4.
INFO:Xst:2260 - The FF/Latch <dbus<2>LogicTrst18_SW0_SW0_FRB> in Unit <top> is equivalent to the following 3 FFs/Latches : <dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB> 
INFO:Xst:2261 - The FF/Latch <dbus<2>LogicTrst18_SW0_SW0_FRB> in Unit <top> is equivalent to the following 3 FFs/Latches, which will be removed : <dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB> 

Pipelining and Register Balancing Report ...

Processing Unit <top> :
        Register(s) execunit/acc_0 has(ve) been forward balanced into : execunit/adder/aneg/Madd__not0003<0>1_FRB.
        Register(s) execunit/halt_not000111_FRB ir_8 execunit/memwrite_or000011_FRB ir_11 has(ve) been forward balanced into : dbus<2>LogicTrst18_SW0_SW0_FRB.
        Register(s) execunit/memwrite_or000011_FRB ir_8 ir_11 execunit/halt_not000111_FRB has(ve) been forward balanced into : dbus<0>LogicTrst11_SW0_SW0_FRB.
        Register(s) ir_9 ir_10 ir_11 has(ve) been forward balanced into : execunit/memwrite_or000011_FRB.
        Register(s) ir_9 ir_10 ir_8 has(ve) been forward balanced into : execunit/halt_not000111_FRB.
        Register(s) execunit/acc_10 has(ve) been backward balanced into : execunit/acc_10_BRB0 execunit/acc_10_BRB3 execunit/acc_10_BRB4 execunit/acc_10_BRB5.
        Register(s) execunit/acc_11 has(ve) been backward balanced into : execunit/acc_11_BRB0 execunit/acc_11_BRB1 execunit/acc_11_BRB2 execunit/acc_11_BRB3 execunit/acc_11_BRB4 execunit/acc_11_BRB6 execunit/acc_11_BRB7.
        Register(s) execunit/acc_12 has(ve) been backward balanced into : execunit/acc_12_BRB0 execunit/acc_12_BRB2 execunit/acc_12_BRB3 execunit/acc_12_BRB4 execunit/acc_12_BRB5 execunit/acc_12_BRB6.
        Register(s) execunit/acc_13 has(ve) been backward balanced into : execunit/acc_13_BRB0 execunit/acc_13_BRB1 execunit/acc_13_BRB2 execunit/acc_13_BRB3 execunit/acc_13_BRB4 execunit/acc_13_BRB7 .
        Register(s) execunit/acc_14 has(ve) been backward balanced into : execunit/acc_14_BRB3 execunit/acc_14_BRB6 execunit/acc_14_BRB7 .
        Register(s) execunit/acc_15 has(ve) been backward balanced into : execunit/acc_15_BRB2 execunit/acc_15_BRB3 execunit/acc_15_BRB6 execunit/acc_15_BRB7 execunit/acc_15_BRB11 execunit/acc_15_BRB12 execunit/acc_15_BRB13.
        Register(s) execunit/acc_16 has(ve) been backward balanced into : execunit/acc_16_BRB1 execunit/acc_16_BRB3 execunit/acc_16_BRB4 execunit/acc_16_BRB5 execunit/acc_16_BRB8 execunit/acc_16_BRB10 execunit/acc_16_BRB11 execunit/acc_16_BRB16 execunit/acc_16_BRB17.
        Register(s) execunit/acc_4 has(ve) been backward balanced into : execunit/acc_4_BRB0 execunit/acc_4_BRB3 execunit/acc_4_BRB4 execunit/acc_4_BRB5.
        Register(s) execunit/acc_5 has(ve) been backward balanced into : execunit/acc_5_BRB0 execunit/acc_5_BRB3 execunit/acc_5_BRB4 execunit/acc_5_BRB5.
        Register(s) execunit/acc_6 has(ve) been backward balanced into : execunit/acc_6_BRB0 execunit/acc_6_BRB3 execunit/acc_6_BRB4 execunit/acc_6_BRB5.
        Register(s) execunit/acc_7 has(ve) been backward balanced into : execunit/acc_7_BRB0 execunit/acc_7_BRB3 execunit/acc_7_BRB4 execunit/acc_7_BRB5.
        Register(s) execunit/acc_8 has(ve) been backward balanced into : execunit/acc_8_BRB0 execunit/acc_8_BRB3 execunit/acc_8_BRB4 execunit/acc_8_BRB5.
        Register(s) execunit/acc_9 has(ve) been backward balanced into : execunit/acc_9_BRB0 execunit/acc_9_BRB3 execunit/acc_9_BRB4 .
Unit <top> processed.
FlipFlop ir_11 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 237
 Flip-Flops                                            : 237

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 32

Cell Usage :
# BELS                             : 952
#      GND                         : 3
#      INV                         : 11
#      LUT1                        : 34
#      LUT2                        : 59
#      LUT2_L                      : 1
#      LUT3                        : 135
#      LUT3_D                      : 4
#      LUT3_L                      : 2
#      LUT4                        : 312
#      LUT4_D                      : 18
#      LUT4_L                      : 8
#      MUXCY                       : 166
#      MUXF5                       : 48
#      VCC                         : 2
#      XORCY                       : 149
# FlipFlops/Latches                : 237
#      FD                          : 11
#      FDC                         : 79
#      FDCE                        : 3
#      FDE                         : 83
#      FDP                         : 25
#      FDPE                        : 2
#      FDR                         : 1
#      FDRE                        : 18
#      FDRS                        : 10
#      FDS                         : 1
#      FDSE                        : 4
# RAMS                             : 1
#      RAMB16                      : 1
# Clock Buffers                    : 3
#      BUFG                        : 3
# IO Buffers                       : 32
#      IBUF                        : 12
#      IBUFG                       : 1
#      OBUF                        : 19
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1000ft256-4 

 Number of Slices:                      317  out of   7680     4%  
 Number of Slice Flip Flops:            237  out of  15360     1%  
 Number of 4 input LUTs:                584  out of  15360     3%  
 Number of IOs:                          32
 Number of bonded IOBs:                  32  out of    173    18%  
 Number of BRAMs:                         1  out of     24     4%  
 Number of GCLKs:                         3  out of      8    37%  
 Number of DCMs:                          1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | clockdll/DCM_INST:CLKFX| 2     |
clkdiv1                            | BUFG                   | 236   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+-----------------------------------+-------+
Control Signal                     | Buffer(FF name)                   | Load  |
-----------------------------------+-----------------------------------+-------+
reset(reset:Q)                     | NONE(execunit/out/leds/oDigitLeft)| 109   |
-----------------------------------+-----------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 29.957ns (Maximum Frequency: 33.381MHz)
   Minimum input arrival time before clock: 10.357ns
   Maximum output required time after clock: 11.416ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.679ns (frequency: 595.692MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.623ns (Levels of Logic = 0)
  Source:            clkdiv (FF)
  Destination:       clkdiv (FF)
  Source Clock:      clk rising 0.6X
  Destination Clock: clk rising 0.6X

  Data Path: clkdiv to clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.877  clkdiv (clkdiv1)
     FDR:R                     1.026          clkdiv
    ----------------------------------------
    Total                      2.623ns (1.746ns logic, 0.877ns route)
                                       (66.6% logic, 33.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkdiv1'
  Clock period: 29.957ns (frequency: 33.381MHz)
  Total number of paths / destination ports: 206561462 / 375
-------------------------------------------------------------------------
Delay:               29.957ns (Levels of Logic = 24)
  Source:            clkphase_0 (FF)
  Destination:       execunit/acc_3 (FF)
  Source Clock:      clkdiv1 rising
  Destination Clock: clkdiv1 rising

  Data Path: clkphase_0 to execunit/acc_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q             13   0.720   1.509  clkphase_0 (clkphase_0)
     LUT4:I0->O           15   0.551   1.256  ir_cmp_eq00001_1 (ir_cmp_eq00001)
     LUT3:I2->O           18   0.551   1.443  xmemoe1 (xmemoe)
     LUT4:I3->O            7   0.551   1.405  dbus<2>LogicTrst18 (dbus<2>)
     LUT2:I0->O            1   0.551   0.000  execunit/adder/bneg/Madd__sub0002_xor<2>11 (execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_lut<2>)
     MUXCY:S->O            1   0.500   0.000  execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_cy<2> (execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_cy<2>)
     XORCY:CI->O           4   0.904   0.943  execunit/adder/bneg/negplus/inc/add1/Madd_temp_Madd_xor<3> (execunit/adder/bneg/negplus/inc/add1/temp<3>)
     LUT4:I3->O            1   0.551   0.827  execunit/adder/bneg/y_1_mux000066 (execunit/adder/bneg/y_1_mux000066)
     LUT4:I3->O            1   0.551   0.000  execunit/adder/adder/add1/Madd_temp_Madd_lut<1> (execunit/adder/adder/add1/Madd_temp_Madd_lut<1>)
     MUXCY:S->O            1   0.500   0.000  execunit/adder/adder/add1/Madd_temp_Madd_cy<1> (execunit/adder/adder/add1/Madd_temp_Madd_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  execunit/adder/adder/add1/Madd_temp_Madd_cy<2> (execunit/adder/adder/add1/Madd_temp_Madd_cy<2>)
     XORCY:CI->O           7   0.904   1.092  execunit/adder/adder/add1/Madd_temp_Madd_xor<3> (execunit/adder/adder/add1/temp<3>)
     LUT4:I3->O            1   0.551   0.801  execunit/adder/adder/add1/cyout1 (execunit/adder/adder/c0)
     MUXCY:CI->O           1   0.064   0.000  execunit/adder/adder/add2/Madd_temp_Madd_cy<0> (execunit/adder/adder/add2/Madd_temp_Madd_cy<0>)
     XORCY:CI->O           7   0.904   1.261  execunit/adder/adder/add2/Madd_temp_Madd_xor<1> (execunit/adder/adder/add2/temp<1>)
     LUT4:I1->O            1   0.551   0.801  execunit/adder/adder/add2/cyout1 (execunit/adder/adder/c1)
     MUXCY:CI->O           1   0.064   0.000  execunit/adder/adder/add3/Madd_temp_Madd_cy<0> (execunit/adder/adder/add3/Madd_temp_Madd_cy<0>)
     XORCY:CI->O           7   0.904   1.261  execunit/adder/adder/add3/Madd_temp_Madd_xor<1> (execunit/adder/adder/add3/temp<1>)
     LUT4:I1->O            1   0.551   0.801  execunit/adder/adder/add3/cyout1 (execunit/adder/adder/c2)
     MUXCY:CI->O           1   0.064   0.000  execunit/adder/adder/add4/Madd_temp_Madd_cy<0> (execunit/adder/adder/add4/Madd_temp_Madd_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  execunit/adder/adder/add4/Madd_temp_Madd_cy<1> (execunit/adder/adder/add4/Madd_temp_Madd_cy<1>)
     XORCY:CI->O           8   0.904   1.151  execunit/adder/adder/add4/Madd_temp_Madd_xor<2> (execunit/adder/adder/add4/temp<2>)
     LUT3:I2->O            1   0.551   0.827  execunit/adder/adder/add4/cyout1_SW0 (N108)
     LUT4:I3->O           10   0.551   1.134  execunit/adder/adder/Madd_z<16>_Madd_xor<0>11 (execunit/adder/zout<16>)
     MUXF5:S->O            1   0.621   0.000  execunit/acc_mux0000<3>107 (execunit/acc_mux0000<3>)
     FDE:D                     0.203          execunit/acc_3
    ----------------------------------------
    Total                     29.957ns (13.445ns logic, 16.512ns route)
                                       (44.9% logic, 55.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkdiv1'
  Total number of paths / destination ports: 29 / 26
-------------------------------------------------------------------------
Offset:              10.357ns (Levels of Logic = 7)
  Source:            sw<0> (PAD)
  Destination:       execunit/acc_0 (FF)
  Destination Clock: clkdiv1 rising

  Data Path: sw<0> to execunit/acc_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   1.216  sw_0_IBUF (sw_0_IBUF)
     LUT4:I0->O            1   0.551   1.140  execunit/acc_mux0000<0>8 (execunit/acc_mux0000<0>8)
     LUT4:I0->O            1   0.551   0.827  execunit/acc_mux0000<0>52_SW0 (N340)
     LUT4:I3->O            1   0.551   0.869  execunit/acc_mux0000<0>52 (execunit/acc_mux0000<0>52)
     LUT4:I2->O            2   0.551   0.903  execunit/acc_mux0000<0>84 (execunit/acc_mux0000<0>84)
     LUT4:I3->O            2   0.551   1.072  execunit/adder/zneg/y_0_mux00001_SW0 (N260)
     LUT4:I1->O            1   0.551   0.000  execunit/acc_mux0000<0>112 (execunit/acc_mux0000<0>)
     FDE:D                     0.203          execunit/acc_0
    ----------------------------------------
    Total                     10.357ns (4.330ns logic, 6.027ns route)
                                       (41.8% logic, 58.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv1'
  Total number of paths / destination ports: 59 / 19
-------------------------------------------------------------------------
Offset:              11.416ns (Levels of Logic = 3)
  Source:            execunit/memwrite (FF)
  Destination:       led<4> (PAD)
  Source Clock:      clkdiv1 rising

  Data Path: execunit/memwrite to led<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            14   0.720   1.255  execunit/memwrite (execunit/memwrite)
     LUT3_D:I2->O         18   0.551   1.612  execunit/dbus_and00001 (execunit/dbus_and0000)
     LUT4:I1->O            8   0.551   1.083  memaddr<4>1 (led_4_OBUF)
     OBUF:I->O                 5.644          led_4_OBUF (led<4>)
    ----------------------------------------
    Total                     11.416ns (7.466ns logic, 3.950ns route)
                                       (65.4% logic, 34.6% route)

=========================================================================


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 11.44 secs
 
--> 


Total memory usage is 371320 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   20 (   0 filtered)
Number of infos    :    4 (   0 filtered)