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[/] [vtach/] [trunk/] [top.twr] - Rev 2
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--------------------------------------------------------------------------------Release 13.2 Trace (lin64)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved./opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -filter/home/alw/projects/vtachspartan/iseconfig/filter.filter -intstyle ise -v 3 -s 4-n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf vtach.ucfDesign file: top.ncdPhysical constraint file: top.pcfDevice,package,speed: xc3s1000,ft256,-4 (PRODUCTION 1.39 2011-06-20)Report level: verbose reportEnvironment Variable Effect-------------------- ------NONE No environment variables were set--------------------------------------------------------------------------------INFO:Timing:2752 - To get complete path coverage, use the unconstrained pathsoption. All paths that are not constrained will be reported in theunconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based ona 50 Ohm transmission line loading model. For the details of this model,and for more information on accounting for different loading conditions,please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jittervalue, please add SYSTEM_JITTER constraint to the UCF to modify the ClockUncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and'Phase Error' calculations, these terms will be zero in the ClockUncertainty calculation. Please make appropriate modification toSYSTEM_JITTER to account for the unsupported Discrete Jitter and PhaseError.================================================================================Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 component switching limit errors)Minimum period is 6.000ns.--------------------------------------------------------------------------------Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH 50%;--------------------------------------------------------------------------------Slack: 14.000ns (period - (min low pulse limit / (low pulse / period)))Period: 20.000nsLow pulse: 10.000nsLow pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)Physical resource: clockdll/DCM_INST/CLKINLogical resource: clockdll/DCM_INST/CLKINLocation pin: DCM_X0Y0.CLKINClock network: clockdll/CLKIN_IBUFG--------------------------------------------------------------------------------Slack: 14.000ns (period - (min high pulse limit / (high pulse / period)))Period: 20.000nsHigh pulse: 10.000nsHigh pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)Physical resource: clockdll/DCM_INST/CLKINLogical resource: clockdll/DCM_INST/CLKINLocation pin: DCM_X0Y0.CLKINClock network: clockdll/CLKIN_IBUFG--------------------------------------------------------------------------------Slack: 14.013ns (period - min period limit)Period: 20.000nsMin period limit: 5.987ns (167.029MHz) (Tdcmpc)Physical resource: clockdll/DCM_INST/CLKINLogical resource: clockdll/DCM_INST/CLKINLocation pin: DCM_X0Y0.CLKINClock network: clockdll/CLKIN_IBUFG--------------------------------------------------------------------------------================================================================================Timing constraint: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF"TS_clk * 0.64 HIGH 50%;14 paths analyzed, 14 endpoints analyzed, 0 failing endpoints0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)Minimum period is 7.773ns.--------------------------------------------------------------------------------Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA0), 1 path--------------------------------------------------------------------------------Slack (setup path): 23.477ns (requirement - (data path - clock path skew + uncertainty))Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Requirement: 31.250nsData Path Delay: 7.773ns (Levels of Logic = 3)Clock Path Skew: 0.000nsSource Clock: clkls rising at 0.000nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMaximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ALocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------RAMB16_X1Y4.DOA0 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X75Y36.F4 net (fanout=1) 0.695 mem/outdata<0>SLICE_X75Y36.X Tilo 0.551 execunit/out/val<1>xmemoe1_SW0SLICE_X75Y42.G2 net (fanout=1) 1.006 N103SLICE_X75Y42.Y Tilo 0.551 execunit/adder/bneg/Madd__not0002<0>dbus<0>LogicTrst4SLICE_X74Y43.F2 net (fanout=3) 0.212 dbus<0>LogicTrst4SLICE_X74Y43.X Tilo 0.608 ir<0>dbus<0>LogicTrst18RAMB16_X1Y4.DIA0 net (fanout=3) 1.272 dbus<0>RAMB16_X1Y4.CLKA Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A------------------------------------------------- ---------------------------Total 7.773ns (4.588ns logic, 3.185ns route)(59.0% logic, 41.0% route)--------------------------------------------------------------------------------Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAMB16_X1Y4.DIB8), 1 path--------------------------------------------------------------------------------Slack (setup path): 24.498ns (requirement - (data path - clock path skew + uncertainty))Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAM)Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAM)Requirement: 31.250nsData Path Delay: 6.752ns (Levels of Logic = 1)Clock Path Skew: 0.000nsSource Clock: clkls rising at 0.000nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMaximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.BLocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------RAMB16_X1Y4.DOB8 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.BSLICE_X69Y39.F3 net (fanout=2) 1.163 mem/outdata<9>SLICE_X69Y39.X Tilo 0.551 ir<9>dbus<9>LogicTrstRAMB16_X1Y4.DIB8 net (fanout=10) 2.160 dbus<9>RAMB16_X1Y4.CLKB Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B------------------------------------------------- ---------------------------Total 6.752ns (3.429ns logic, 3.323ns route)(50.8% logic, 49.2% route)--------------------------------------------------------------------------------Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA1), 1 path--------------------------------------------------------------------------------Slack (setup path): 24.512ns (requirement - (data path - clock path skew + uncertainty))Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Requirement: 31.250nsData Path Delay: 6.738ns (Levels of Logic = 2)Clock Path Skew: 0.000nsSource Clock: clkls rising at 0.000nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMaximum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ALocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------RAMB16_X1Y4.DOA1 Tbcko 2.394 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X74Y43.G3 net (fanout=1) 1.156 mem/outdata<1>SLICE_X74Y43.Y Tilo 0.608 ir<0>dbus<1>LogicTrst18_SW1SLICE_X74Y42.F3 net (fanout=2) 0.027 N101SLICE_X74Y42.X Tilo 0.608 ir<1>dbus<1>LogicTrst18RAMB16_X1Y4.DIA1 net (fanout=6) 1.461 dbus<1>RAMB16_X1Y4.CLKA Tbdck 0.484 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A------------------------------------------------- ---------------------------Total 6.738ns (4.094ns logic, 2.644ns route)(60.8% logic, 39.2% route)--------------------------------------------------------------------------------Hold Paths: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH50%;--------------------------------------------------------------------------------Paths for end point clkdiv (SLICE_X40Y95.SR), 1 path--------------------------------------------------------------------------------Slack (hold path): 1.282ns (requirement - (clock path skew + uncertainty - data path))Source: clkdiv (FF)Destination: clkdiv (FF)Requirement: 0.000nsData Path Delay: 1.282ns (Levels of Logic = 0)Clock Path Skew: 0.000nsSource Clock: clkls rising at 31.250nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMinimum Data Path: clkdiv to clkdivLocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------SLICE_X40Y95.YQ Tcko 0.576 clkdiv1clkdivSLICE_X40Y95.SR net (fanout=2) 0.677 clkdiv1SLICE_X40Y95.CLK Tcksr (-Th) -0.029 clkdiv1clkdiv------------------------------------------------- ---------------------------Total 1.282ns (0.605ns logic, 0.677ns route)(47.2% logic, 52.8% route)--------------------------------------------------------------------------------Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA24), 1 path--------------------------------------------------------------------------------Slack (hold path): 3.739ns (requirement - (clock path skew + uncertainty - data path))Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Requirement: 0.000nsData Path Delay: 3.739ns (Levels of Logic = 2)Clock Path Skew: 0.000nsSource Clock: clkls rising at 31.250nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMinimum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ALocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------RAMB16_X1Y4.DOA24 Tbcko 1.915 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X74Y37.G2 net (fanout=1) 0.482 mem/outdata<6>SLICE_X74Y37.Y Tilo 0.486 ir<6>dbus<6>LogicTrst4SLICE_X74Y37.F3 net (fanout=3) 0.029 dbus<6>LogicTrst4SLICE_X74Y37.X Tilo 0.486 ir<6>dbus<6>LogicTrst18RAMB16_X1Y4.DIA24 net (fanout=4) 0.341 dbus<6>RAMB16_X1Y4.CLKA Tbckd (-Th) 0.000 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A------------------------------------------------- ---------------------------Total 3.739ns (2.887ns logic, 0.852ns route)(77.2% logic, 22.8% route)--------------------------------------------------------------------------------Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA9), 1 path--------------------------------------------------------------------------------Slack (hold path): 3.846ns (requirement - (clock path skew + uncertainty - data path))Source: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Destination: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAM)Requirement: 0.000nsData Path Delay: 3.846ns (Levels of Logic = 2)Clock Path Skew: 0.000nsSource Clock: clkls rising at 31.250nsDestination Clock: clkls rising at 31.250nsClock Uncertainty: 0.000nsMinimum Data Path: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A to mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ALocation Delay type Delay(ns) Physical ResourceLogical Resource(s)------------------------------------------------- -------------------RAMB16_X1Y4.DOA9 Tbcko 1.915 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.ASLICE_X75Y35.G4 net (fanout=1) 0.279 mem/outdata<3>SLICE_X75Y35.Y Tilo 0.441 execunit/halt_not000111_FRBdbus<3>LogicTrst18_SW1SLICE_X74Y34.F1 net (fanout=1) 0.194 N92SLICE_X74Y34.X Tilo 0.486 ir<3>dbus<3>LogicTrst18RAMB16_X1Y4.DIA9 net (fanout=5) 0.531 dbus<3>RAMB16_X1Y4.CLKA Tbckd (-Th) 0.000 mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.rammem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A------------------------------------------------- ---------------------------Total 3.846ns (2.842ns logic, 1.004ns route)(73.9% logic, 26.1% route)--------------------------------------------------------------------------------Component Switching Limit Checks: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "clockdll_CLKFX_BUF" TS_clk * 0.64 HIGH50%;--------------------------------------------------------------------------------Slack: 28.518ns (period - (min low pulse limit / (low pulse / period)))Period: 31.250nsLow pulse: 15.625nsLow pulse limit: 1.366ns (Tbpwl)Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKALogical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKALocation pin: RAMB16_X1Y4.CLKAClock network: clkls--------------------------------------------------------------------------------Slack: 28.518ns (period - (min high pulse limit / (high pulse / period)))Period: 31.250nsHigh pulse: 15.625nsHigh pulse limit: 1.366ns (Tbpwh)Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKALogical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKALocation pin: RAMB16_X1Y4.CLKAClock network: clkls--------------------------------------------------------------------------------Slack: 28.518ns (period - min period limit)Period: 31.250nsMin period limit: 2.732ns (366.032MHz) (Tbp)Physical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKALogical resource: mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKALocation pin: RAMB16_X1Y4.CLKAClock network: clkls--------------------------------------------------------------------------------Derived Constraint ReportDerived Constraints for TS_clk+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+| | Period | Actual Period | Timing Errors | Paths Analyzed || Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+|TS_clk | 20.000ns| 6.000ns| 4.975ns| 0| 0| 0| 14|| TS_clockdll_CLKFX_BUF | 31.250ns| 7.773ns| N/A| 0| 0| 14| 0|+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+All constraints were met.Data Sheet report:-----------------All values displayed in nanoseconds (ns)Clock to Setup on destination clock clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+clk | 7.773| | | |---------------+---------+---------+---------+---------+Timing summary:---------------Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)Constraints cover 14 paths, 0 nets, and 43 connectionsDesign statistics:Minimum period: 7.773ns{1} (Maximum frequency: 128.650MHz)------------------------------------Footnotes-----------------------------------1) The minimum period statistic assumes all single cycle delays.Analysis completed Sat May 25 07:43:45 2013--------------------------------------------------------------------------------Trace Settings:-------------------------Trace SettingsPeak Memory Usage: 246 MB