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[/] [vtach/] [trunk/] [top.twx] - Rev 2

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
                                        twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
                                                           NETDELAY | 
                                                           NETSKEW | 
                                                           PATH |
                                                           DEFPERIOD |
                                                           UNCONSTPATH |
                                                           DEFPATH | 
                                                           PATH2SETUP |
                                                           UNCONSTPATH2SETUP | 
                                                           PATHCLASS | 
                                                           PATHDELAY | 
                                                           PERIOD |
                                                           FREQUENCY |
                                                           PATHBLOCK |
                                                           OFFSET |
                                                           OFFSETIN |
                                                           OFFSETINCLOCK | 
                                                           UNCONSTOFFSETINCLOCK |
                                                           OFFSETINDELAY |
                                                           OFFSETINMOD |
                                                           OFFSETOUT |
                                                           OFFSETOUTCLOCK |
                                                           UNCONSTOFFSETOUTCLOCK | 
                                                           OFFSETOUTDELAY |
                                                           OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
                                           twEndPtCnt?,
                                           twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
                                                twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
                                          fDCMJit CDATA #IMPLIED
                                          fPhaseErr CDATA #IMPLIED
                                          sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
                         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
                                          best CDATA #IMPLIED requested CDATA #IMPLIED
                                          errors CDATA #IMPLIED
                                          score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 13.2 Trace  (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -filter
/home/alw/projects/vtachspartan/iseconfig/filter.filter -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf vtach.ucf

</twCmdLine><twDesign>top.ncd</twDesign><twDesignPath>top.ncd</twDesignPath><twPCF>top.pcf</twPCF><twPcfPath>top.pcf</twPcfPath><twDevInfo arch="spartan3" pkg="ft256"><twDevName>xc3s1000</twDevName><twSpeedGrade>-4</twSpeedGrade><twSpeedVer>PRODUCTION 1.39 2011-06-20</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="4">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="5">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation.  Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twConst anchorID="6" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_clk = PERIOD &quot;clk&quot; 50 MHz HIGH 50 %;" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 50 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.000</twMinPer></twConstHead><twPinLimitRpt anchorID="7"><twPinLimitBanner>Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP &quot;clk&quot; 50 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="8" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="14.000" period="20.000" constraintValue="10.000" deviceLimit="3.000" physResource="clockdll/DCM_INST/CLKIN" logResource="clockdll/DCM_INST/CLKIN" locationPin="DCM_X0Y0.CLKIN" clockNet="clockdll/CLKIN_IBUFG"/><twPinLimit anchorID="9" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="14.000" period="20.000" constraintValue="10.000" deviceLimit="3.000" physResource="clockdll/DCM_INST/CLKIN" logResource="clockdll/DCM_INST/CLKIN" locationPin="DCM_X0Y0.CLKIN" clockNet="clockdll/CLKIN_IBUFG"/><twPinLimit anchorID="10" type="MINPERIOD" name="Tdcmpc" slack="14.013" period="20.000" constraintValue="20.000" deviceLimit="5.987" freqLimit="167.029" physResource="clockdll/DCM_INST/CLKIN" logResource="clockdll/DCM_INST/CLKIN" locationPin="DCM_X0Y0.CLKIN" clockNet="clockdll/CLKIN_IBUFG"/></twPinLimitRpt></twConst><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="TIMESPEC TS_clk = PERIOD &quot;clk&quot; 50 MHz HIGH 50 %;" ScopeName="">TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP &quot;clockdll_CLKFX_BUF&quot; TS_clk * 0.64 HIGH         50%;</twConstName><twItemCnt>14</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>14</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>7.773</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA0), 1 path
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>23.477</twSlack><twSrc BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twTotPathDel>7.773</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twLogLvls>3</twLogLvls><twSrcSite>RAMB16_X1Y4.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clkls</twSrcClk><twPathDel><twSite>RAMB16_X1Y4.DOA0</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.394</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twPathDel><twSite>SLICE_X75Y36.F4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.695</twDelInfo><twComp>mem/outdata&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X75Y36.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.551</twDelInfo><twComp>execunit/out/val&lt;1&gt;</twComp><twBEL>xmemoe1_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X75Y42.G2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.006</twDelInfo><twComp>N103</twComp></twPathDel><twPathDel><twSite>SLICE_X75Y42.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.551</twDelInfo><twComp>execunit/adder/bneg/Madd__not0002&lt;0&gt;</twComp><twBEL>dbus&lt;0&gt;LogicTrst4</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y43.F2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.212</twDelInfo><twComp>dbus&lt;0&gt;LogicTrst4</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y43.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.608</twDelInfo><twComp>ir&lt;0&gt;</twComp><twBEL>dbus&lt;0&gt;LogicTrst18</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.DIA0</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.272</twDelInfo><twComp>dbus&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKA</twSite><twDelType>Tbdck</twDelType><twDelInfo twEdge="twRising">0.484</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twLogDel>4.588</twLogDel><twRouteDel>3.185</twRouteDel><twTotDel>7.773</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>59.0</twPctLog><twPctRoute>41.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B (RAMB16_X1Y4.DIB8), 1 path
</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>24.498</twSlack><twSrc BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twSrc><twDest BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twDest><twTotPathDel>6.752</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twSrc><twDest BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twDest><twLogLvls>1</twLogLvls><twSrcSite>RAMB16_X1Y4.CLKB</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clkls</twSrcClk><twPathDel><twSite>RAMB16_X1Y4.DOB8</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.394</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twBEL></twPathDel><twPathDel><twSite>SLICE_X69Y39.F3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.163</twDelInfo><twComp>mem/outdata&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X69Y39.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.551</twDelInfo><twComp>ir&lt;9&gt;</twComp><twBEL>dbus&lt;9&gt;LogicTrst</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.DIB8</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">2.160</twDelInfo><twComp>dbus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Tbdck</twDelType><twDelInfo twEdge="twRising">0.484</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B</twBEL></twPathDel><twLogDel>3.429</twLogDel><twRouteDel>3.323</twRouteDel><twTotDel>6.752</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>50.8</twPctLog><twPctRoute>49.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA1), 1 path
</twPathRptBanner><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>24.512</twSlack><twSrc BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twTotPathDel>6.738</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twLogLvls>2</twLogLvls><twSrcSite>RAMB16_X1Y4.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clkls</twSrcClk><twPathDel><twSite>RAMB16_X1Y4.DOA1</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">2.394</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y43.G3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.156</twDelInfo><twComp>mem/outdata&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y43.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.608</twDelInfo><twComp>ir&lt;0&gt;</twComp><twBEL>dbus&lt;1&gt;LogicTrst18_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y42.F3</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.027</twDelInfo><twComp>N101</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y42.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.608</twDelInfo><twComp>ir&lt;1&gt;</twComp><twBEL>dbus&lt;1&gt;LogicTrst18</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.DIA1</twSite><twDelType>net</twDelType><twFanCnt>6</twFanCnt><twDelInfo twEdge="twRising">1.461</twDelInfo><twComp>dbus&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKA</twSite><twDelType>Tbdck</twDelType><twDelInfo twEdge="twRising">0.484</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twLogDel>4.094</twLogDel><twRouteDel>2.644</twRouteDel><twTotDel>6.738</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>60.8</twPctLog><twPctRoute>39.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP &quot;clockdll_CLKFX_BUF&quot; TS_clk * 0.64 HIGH
        50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point clkdiv (SLICE_X40Y95.SR), 1 path
</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>1.282</twSlack><twSrc BELType="FF">clkdiv</twSrc><twDest BELType="FF">clkdiv</twDest><twTotPathDel>1.282</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>clkdiv</twSrc><twDest BELType='FF'>clkdiv</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X40Y95.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">clkls</twSrcClk><twPathDel><twSite>SLICE_X40Y95.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.576</twDelInfo><twComp>clkdiv1</twComp><twBEL>clkdiv</twBEL></twPathDel><twPathDel><twSite>SLICE_X40Y95.SR</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.677</twDelInfo><twComp>clkdiv1</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X40Y95.CLK</twSite><twDelType>Tcksr</twDelType><twDelInfo twEdge="twFalling">0.029</twDelInfo><twComp>clkdiv1</twComp><twBEL>clkdiv</twBEL></twPathDel><twLogDel>0.605</twLogDel><twRouteDel>0.677</twRouteDel><twTotDel>1.282</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>47.2</twPctLog><twPctRoute>52.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA24), 1 path
</twPathRptBanner><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>3.739</twSlack><twSrc BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twTotPathDel>3.739</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twLogLvls>2</twLogLvls><twSrcSite>RAMB16_X1Y4.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">clkls</twSrcClk><twPathDel><twSite>RAMB16_X1Y4.DOA24</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">1.915</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y37.G2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.482</twDelInfo><twComp>mem/outdata&lt;6&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y37.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.486</twDelInfo><twComp>ir&lt;6&gt;</twComp><twBEL>dbus&lt;6&gt;LogicTrst4</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y37.F3</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.029</twDelInfo><twComp>dbus&lt;6&gt;LogicTrst4</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y37.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.486</twDelInfo><twComp>ir&lt;6&gt;</twComp><twBEL>dbus&lt;6&gt;LogicTrst18</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.DIA24</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twFalling">0.341</twDelInfo><twComp>dbus&lt;6&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X1Y4.CLKA</twSite><twDelType>Tbckd</twDelType><twDelInfo twEdge="twFalling">0.000</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twLogDel>2.887</twLogDel><twRouteDel>0.852</twRouteDel><twTotDel>3.739</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>77.2</twPctLog><twPctRoute>22.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A (RAMB16_X1Y4.DIA9), 1 path
</twPathRptBanner><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>3.846</twSlack><twSrc BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType="RAM">mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twTotPathDel>3.846</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twSrc><twDest BELType='RAM'>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twDest><twLogLvls>2</twLogLvls><twSrcSite>RAMB16_X1Y4.CLKA</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">clkls</twSrcClk><twPathDel><twSite>RAMB16_X1Y4.DOA9</twSite><twDelType>Tbcko</twDelType><twDelInfo twEdge="twRising">1.915</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twPathDel><twSite>SLICE_X75Y35.G4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.279</twDelInfo><twComp>mem/outdata&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X75Y35.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.441</twDelInfo><twComp>execunit/halt_not000111_FRB</twComp><twBEL>dbus&lt;3&gt;LogicTrst18_SW1</twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y34.F1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.194</twDelInfo><twComp>N92</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y34.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.486</twDelInfo><twComp>ir&lt;3&gt;</twComp><twBEL>dbus&lt;3&gt;LogicTrst18</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.DIA9</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twFalling">0.531</twDelInfo><twComp>dbus&lt;3&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB16_X1Y4.CLKA</twSite><twDelType>Tbckd</twDelType><twDelInfo twEdge="twFalling">0.000</twDelInfo><twComp>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</twComp><twBEL>mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A</twBEL></twPathDel><twLogDel>2.842</twLogDel><twRouteDel>1.004</twRouteDel><twTotDel>3.846</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">clkls</twDestClk><twPctLog>73.9</twPctLog><twPctRoute>26.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="24"><twPinLimitBanner>Component Switching Limit Checks: TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP &quot;clockdll_CLKFX_BUF&quot; TS_clk * 0.64 HIGH
        50%;</twPinLimitBanner><twPinLimit anchorID="25" type="MINLOWPULSE" name="Tbpwl" slack="28.518" period="31.250" constraintValue="15.625" deviceLimit="1.366" physResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA" logResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA" locationPin="RAMB16_X1Y4.CLKA" clockNet="clkls"/><twPinLimit anchorID="26" type="MINHIGHPULSE" name="Tbpwh" slack="28.518" period="31.250" constraintValue="15.625" deviceLimit="1.366" physResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA" logResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA" locationPin="RAMB16_X1Y4.CLKA" clockNet="clkls"/><twPinLimit anchorID="27" type="MINPERIOD" name="Tbp" slack="28.518" period="31.250" constraintValue="31.250" deviceLimit="2.732" freqLimit="366.032" physResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram/CLKA" logResource="mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A/CLKA" locationPin="RAMB16_X1Y4.CLKA" clockNet="clkls"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="28"><twConstRollup name="TS_clk" fullName="TS_clk = PERIOD TIMEGRP &quot;clk&quot; 50 MHz HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="6.000" actualRollup="4.975" errors="0" errorRollup="0" items="0" itemsRollup="14"/><twConstRollup name="TS_clockdll_CLKFX_BUF" fullName="TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP &quot;clockdll_CLKFX_BUF&quot; TS_clk * 0.64 HIGH         50%;" type="child" depth="1" requirement="31.250" prefType="period" actual="7.773" actualRollup="N/A" errors="0" errorRollup="0" items="14" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="29">0</twUnmetConstCnt><twDataSheet anchorID="30" twNameLen="15"><twClk2SUList anchorID="31" twDestWidth="3"><twDest>clk</twDest><twClk2SU><twSrc>clk</twSrc><twRiseRise>7.773</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="32"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>14</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>43</twConnCnt></twConstCov><twStats anchorID="33"><twMinPer>7.773</twMinPer><twFootnote number="1" /><twMaxFreq>128.650</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Sat May 25 07:43:45 2013 </twTimestamp></twFoot><twClientInfo anchorID="34"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 246 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

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