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Release 13.2 Map O.61xd (lin64)Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line : map -filter iseconfig/filter.filter -intstyle ise -pxc3s1000-ft256-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplicationon -cm speed -ir off -ignore_keep_hierarchy -pr off -power off -o top_map.ncdtop.ngd top.pcfTarget Device : xc3s1000Target Package : ft256Target Speed : -4Mapper Version : spartan3 -- $Revision: 1.55 $Mapped Date : Sat May 25 07:43:29 2013Design Summary--------------Number of errors: 0Number of warnings: 51Logic Utilization:Number of Slice Flip Flops: 237 out of 15,360 1%Number of 4 input LUTs: 557 out of 15,360 3%Logic Distribution:Number of occupied Slices: 347 out of 7,680 4%Number of Slices containing only related logic: 347 out of 347 100%Number of Slices containing unrelated logic: 0 out of 347 0%*See NOTES below for an explanation of the effects of unrelated logic.Total Number of 4 input LUTs: 597 out of 15,360 3%Number used as logic: 557Number used as a route-thru: 40The Slice Logic Distribution report is not meaningful if the design isover-mapped for a non-slice resource or if Placement fails.Number of bonded IOBs: 32 out of 173 18%Number of RAMB16s: 1 out of 24 4%Number of BUFGMUXs: 3 out of 8 37%Number of DCMs: 1 out of 4 25%Average Fanout of Non-Clock Nets: 3.29Peak Memory Usage: 429 MBTotal REAL time to MAP completion: 7 secsTotal CPU time to MAP completion: 7 secsTable of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Timing ReportSection 11 - Configuration String InformationSection 12 - Control Set InformationSection 13 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Security:42 - Your software subscription period has lapsed. Your currentversion of Xilinx tools will continue to function, but you no longer qualify forXilinx software updates or new releases.WARNING:PhysDesignRules:812 - Dangling pin <DOA2> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA3> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA4> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA5> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA6> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA7> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA10> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA11> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA12> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA13> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA14> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA15> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA18> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA19> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA20> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA21> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA22> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA23> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA25> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA26> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA27> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA28> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA29> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA30> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOA31> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.A>:<RAMB16_RAMB16A>.WARNING:PhysDesignRules:812 - Dangling pin <DOB2> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB3> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB4> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB5> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB6> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB7> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB9> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB10> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB11> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB12> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB13> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB14> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB15> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB18> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB19> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB20> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB21> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB22> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB23> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB25> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB26> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB27> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB28> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB29> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB30> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.WARNING:PhysDesignRules:812 - Dangling pin <DOB31> onblock:<mem/ram/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram.B>:<RAMB16_RAMB16B>.Section 3 - Informational-------------------------INFO:Security:54 - 'xc3s1000' is a WebPack part.INFO:MapLib:562 - No environment variables are currently set.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to1.260 Volts)INFO:Pack:1650 - Map created a placed design.INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performancewith the CLKFX and CLKFX180 outputs of the DCM comp clockdll/DCM_INST,consult the device Interactive Data Sheet.Section 4 - Removed Logic Summary---------------------------------4 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCGND mem/ram/XST_GNDVCC mem/ram/XST_VCCTo enable printing of redundant blocks removed and signals merged, set thedetailed map report option and rerun map.Section 6 - IOB Properties--------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Term | Strength | Rate | | | Delay |+---------------------------------------------------------------------------------------------------------------------------------------------------------+| clk | IOB | INPUT | LVCMOS25 | | | | | | || ds0 | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || ds1 | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || ds2 | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || ds3 | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || extreset | IOB | INPUT | LVCMOS25 | | | | | | || led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || pb0 | IOB | INPUT | LVCMOS25 | | | | | | || pb1 | IOB | INPUT | LVCMOS25 | | | | | | || pb2 | IOB | INPUT | LVCMOS25 | | | | | | || segA | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segB | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segC | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segD | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segE | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segF | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || segG | IOB | OUTPUT | LVCMOS25 | | 12 | FAST | | | || sw<0> | IOB | INPUT | LVCMOS25 | | | | | | || sw<1> | IOB | INPUT | LVCMOS25 | | | | | | || sw<2> | IOB | INPUT | LVCMOS25 | | | | | | || sw<3> | IOB | INPUT | LVCMOS25 | | | | | | || sw<4> | IOB | INPUT | LVCMOS25 | | | | | | || sw<5> | IOB | INPUT | LVCMOS25 | | | | | | || sw<6> | IOB | INPUT | LVCMOS25 | | | | | | || sw<7> | IOB | INPUT | LVCMOS25 | | | | | | |+---------------------------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Timing Report--------------------------A logic-level (pre-route) timing report can be generated by using Xilinx statictiming analysis tools, Timing Analyzer (GUI) or TRCE (command line), with themapped NCD and PCF files. Please note that this timing report will be generatedusing estimated delay information. For accurate numbers, please generate atiming report with the post Place and Route NCD file.For more information about the Timing Analyzer, consult the Xilinx TimingAnalyzer Reference Manual; for more information about TRCE, consult the XilinxCommand Line Tools User Guide "TRACE" chapter.Section 11 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 12 - Control Set Information------------------------------------No control set information for this architecture.Section 13 - Utilization by Hierarchy-------------------------------------Use the "-detail" map option to print out the Utilization by Hierarchy section.