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##### >>>   UCF File for Xilinx Spartan-3 FPGA Board   <<< #####
### Created by Spartan-3 UCF Generator on 12/28/2005 at 12:26
### Spartan-3 Clock Oscillator:
### Spartan-3 Pushbutton Switches:
### Spartan-3 Slide Switches:
### Spartan-3 Discrete LEDs:
### Spartan-3 7-Segment LED:   digit enables:
### Spartan-3 7-Segment LED:   segment enables:
### Spartan-3 SRAM:Enables for IC10:
### Spartan-3 SRAM:Enables for both IC10 and IC11:
### Spartan-3 SRAM:Address for both IC10 and IC11:
### Spartan-3 SRAM:Data for IC10:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
# CLK - 50MHz oscillator
NET "clk" LOC = T9;
# right digit (active low)
NET "ds0" LOC = D14;
# middle right digit (active low)
NET "ds1" LOC = G14;
# middle left digit (active low)
NET "ds2" LOC = F14;
# left digit (active low)
NET "ds3" LOC = E13;
# LED display segment a (active low)
NET "segA" LOC = E14;
# LED display segment b (active low)
NET "segB" LOC = G13;
# LED display segment c (active low)
NET "segC" LOC = N15;
# LED display segment d (active low)
NET "segD" LOC = P15;
# LED display segment e (active low)
NET "segE" LOC = R16;
# LED display segment f (active low)
NET "segF" LOC = F13;
# LED display segment g (active low)
NET "segG" LOC = N16;
#NET "dp"  LOC = "P16"  ; # LED display decimal point (active low)
# LD0 (active high)
NET "led[0]" LOC = K12;
# LD1 (active high)
NET "led[1]" LOC = P14;
# LD2 (active high)
NET "led[2]" LOC = L12;
# LD3 (active high)
NET "led[3]" LOC = N14;
# LD4 (active high)
NET "led[4]" LOC = P13;
# LD5 (active high)
NET "led[5]" LOC = N12;
# LD6 (active high)
NET "led[6]" LOC = P12;
# LD7 (active high)
NET "led[7]" LOC = P11;
# BTN3 (active high)
NET "extreset" LOC = L14;
# BTN2 (active high)
NET "pb2" LOC = L13;
# BTN1 (active high)
NET "pb1" LOC = M14;
# BTN0 (active high)
NET "pb0" LOC = M13;
#NET "serialin"  LOC = "T13"  ;
#NET "serialout" LOC = "R13"  ;
# SW0 (active high when up)
NET "sw[0]" LOC = F12;
# SW1 (active high when up)
NET "sw[1]" LOC = G12;
# SW2 (active high when up)
NET "sw[2]" LOC = H14;
# SW3 (active high when up)
NET "sw[3]" LOC = H13;
# SW4 (active high when up)
NET "sw[4]" LOC = J14;
# SW5 (active high when up)
NET "sw[5]" LOC = J13;
# SW6 (active high when up)
NET "sw[6]" LOC = K14;
# SW7 (active high when up)
NET "sw[7]" LOC = K13;
#NET "xmaddress[0]"  LOC = "L5"  ; # A0
#NET "xmaddress[10]"  LOC = "G5"  ; # A10
#NET "xmaddress[11]"  LOC = "H3"  ; # A11
#NET "xmaddress[12]"  LOC = "H4"  ; # A12
#NET "xmaddress[13]"  LOC = "J4"  ; # A13
#NET "xmaddress[14]"  LOC = "J3"  ; # A14
#NET "xmaddress[15]"  LOC = "K3"  ; # A15
#NET "xmaddress[16]"  LOC = "K5"  ; # A16
#NET "xmaddress[17]"  LOC = "L3"  ; # A17
#NET "xmaddress[1]"  LOC = "N3"  ; # A1
#NET "xmaddress[2]"  LOC = "M4"  ; # A2
#NET "xmaddress[3]"  LOC = "M3"  ; # A3
#NET "xmaddress[4]"  LOC = "L4"  ; # A4
#NET "xmaddress[5]"  LOC = "G4"  ; # A5
#NET "xmaddress[6]"  LOC = "F3"  ; # A6
#NET "xmaddress[7]"  LOC = "F4"  ; # A7
#NET "xmaddress[8]"  LOC = "E3"  ; # A8
#NET "xmaddress[9]"  LOC = "E4"  ; # A9
#NET "xmce"  LOC = "P7"  ; # CE1 - chip enable (active low)
#NET "xmdata[0]"  LOC = "N7"  ; # D0
#NET "xmdata[10]"  LOC = "F2"  ; # D10
#NET "xmdata[11]"  LOC = "H1"  ; # D11
#NET "xmdata[12]"  LOC = "J2"  ; # D12
#NET "xmdata[13]"  LOC = "L2"  ; # D13
#NET "xmdata[14]"  LOC = "P1"  ; # D14
#NET "xmdata[15]"  LOC = "R1"  ; # D15
#NET "xmdata[1]"  LOC = "T8"  ; # D1
#NET "xmdata[2]"  LOC = "R6"  ; # D2
#NET "xmdata[3]"  LOC = "T5"  ; # D3
#NET "xmdata[4]"  LOC = "R5"  ; # D4
#NET "xmdata[5]"  LOC = "C2"  ; # D5
#NET "xmdata[6]"  LOC = "C1"  ; # D6
#NET "xmdata[7]"  LOC = "B1"  ; # D7
#NET "xmdata[8]"  LOC = "D3"  ; # D8
#NET "xmdata[9]"  LOC = "P8"  ; # D9
#NET "xmlb"  LOC = "P6"  ; # LB1 - lower byte enable (active low)
#NET "xmsend"  LOC = "K4"  ; # OE - output enable (active low)
#NET "xmub"  LOC = "T4"  ; # UB1 - upper byte enable (active low)
#NET "xmwrite"  LOC = "G3"  ; # WE - write enable (active low)
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
CONFIG PROHIBIT = C3;
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = D1;
CONFIG PROHIBIT = E2;
CONFIG PROHIBIT = E1;
CONFIG PROHIBIT = F5;
CONFIG PROHIBIT = G2;
CONFIG PROHIBIT = G1;
CONFIG PROHIBIT = J1;
CONFIG PROHIBIT = K1;
CONFIG PROHIBIT = K2;
CONFIG PROHIBIT = M1;
CONFIG PROHIBIT = M2;
CONFIG PROHIBIT = N1;
CONFIG PROHIBIT = N2;
CONFIG PROHIBIT = P2;
CONFIG PROHIBIT = M16;
CONFIG PROHIBIT = M15;
CONFIG PROHIBIT = T14;
CONFIG PROHIBIT = P5;
CONFIG PROHIBIT = N5;
CONFIG PROHIBIT = R9;
CONFIG PROHIBIT = T10;
CONFIG PROHIBIT = N10;
CONFIG PROHIBIT = R11;
CONFIG PROHIBIT = T12;
CONFIG PROHIBIT = R12;
CONFIG PROHIBIT = R4;
#PACE: End of Constraints generated by PACE
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50 %;


# PlanAhead Generated IO constraints 

NET "led[0]" IOSTANDARD = LVCMOS25;
NET "led[1]" IOSTANDARD = LVCMOS25;
NET "led[2]" IOSTANDARD = LVCMOS25;
NET "led[3]" IOSTANDARD = LVCMOS25;
NET "led[4]" IOSTANDARD = LVCMOS25;
NET "led[5]" IOSTANDARD = LVCMOS25;
NET "led[6]" IOSTANDARD = LVCMOS25;
NET "led[7]" IOSTANDARD = LVCMOS25;
NET "ds0" SLEW = FAST;
NET "ds1" SLEW = FAST;
NET "ds2" SLEW = FAST;
NET "ds3" SLEW = FAST;
NET "led[0]" SLEW = FAST;
NET "led[1]" SLEW = FAST;
NET "led[2]" SLEW = FAST;
NET "led[3]" SLEW = FAST;
NET "led[4]" SLEW = FAST;
NET "led[5]" SLEW = FAST;
NET "led[6]" SLEW = FAST;
NET "led[7]" SLEW = FAST;
NET "segA" SLEW = FAST;
NET "segB" SLEW = FAST;
NET "segC" SLEW = FAST;
NET "segD" SLEW = FAST;
NET "segE" SLEW = FAST;
NET "segF" SLEW = FAST;
NET "segG" SLEW = FAST;
NET "sw[0]" SLEW = FAST;
NET "sw[1]" SLEW = FAST;
NET "sw[2]" SLEW = FAST;
NET "sw[3]" SLEW = FAST;
NET "sw[4]" SLEW = FAST;
NET "sw[5]" SLEW = FAST;
NET "sw[6]" SLEW = FAST;
NET "sw[7]" SLEW = FAST;