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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [make/] [syn_s3_speed.opt] - Rev 2
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FLOWTYPE = FPGA_SYNTHESIS;
#########################################################
## Filename: xst_vhdl.opt
##
## VHDL Option File for XST targeted for speed
## This works for FPGA devices.
##
## Version: 8.1.1
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_vhdl_speed.opt,v 1.13 2004/10/01 22:29:20 rvklair Exp $
#########################################################
# Options for XST
#
#
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
#
# The options listed under ParamFile are the XST Properties that can be set by the
# user. To turn on an option, uncomment by removing the '#' in front of the switch.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt VHDL"; # Input Format
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2";
"-uc <design>.xcf"; # Constraint File name
#"-case maintain"; # Specifies how to handle source name case
# upper, lower
#"-keep_hierarchy NO"; # Prevents optimization across module boundaries
# CPLD default YES, FPGA default NO
#"-write_timing_constraints NO"; # Write Timing Constraints
# YES, NO
#"-cross_clock_analysis NO"; # Cross Clock Option
# YES, NO
#"-iobuf YES"; # Add I/O Buffers to top level portS
# YES, NO
#
# The following are HDL Options
#
# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2
#
#"-register_balancing NO"; # Register Balancing
# YES, NO, Forward, Backward
#"-move_first_stage YES"; # Move First Flip-Flop Stage
# YES, NO
#"-move_last_stage YES"; # Move Last Flip-Flop Stage
# YES, NO
End ParamFile
End Program xst
#
# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options
#
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