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# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $
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[xst]
INFO:.*Mux is complete : default of case is discarded

Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'

Node <TST/R_REGS.tx2data_\d*> of sequential type is unconnected
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.datl_\d*> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.dath_\d*> of sequential type is unconnected

Signal <FX2_TX2DATA> is assigned but never used

Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used

Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used

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[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration

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[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*

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[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design

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[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete