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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [sys_gen/] [tst_rlink/] [nexys2/] [sys_tst_rlink_n2.vhd] - Rev 17
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-- $Id: sys_tst_rlink_n2.vhd 465 2012-12-27 21:29:38Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_rlink_n2 - syn -- Description: rlink tester design for nexys2 -- -- Dependencies: vlib/xlib/dcm_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus -- vlib/rlink/rlink_sp1c -- rbd_tst_rlink -- vlib/rbus/rb_sres_or_2 -- vlib/nxcramlib/nx_cram_dummy -- -- Test bench: tb/tb_tst_rlink_n2 -- -- Target Devices: generic -- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5 -- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8 -- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2 -- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8 -- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7 -- -- Revision History: -- Date Rev Version Comment -- 2011-12-23 444 1.2 remove clksys output hack -- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c -- 2011-11-26 433 1.1.5 use nx_cram_dummy now -- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage -- 2011-11-17 426 1.1.3 use dcm_sfs now -- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob -- 2011-07-08 390 1.1.1 use now sn_humanio -- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level -- 2010-12-29 351 1.0 Initial version ------------------------------------------------------------------------------ -- Usage of Nexys 2 Switches, Buttons, LEDs: -- -- SWI(7:2) no function (only connected to sn_humanio_rbus) -- (1) 1 enable XON -- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob -- 1 -> Pmod B/top RS232 port / -- -- LED(7) SER_MONI.abact -- (6:2) no function (only connected to sn_humanio_rbus) -- (0) timer 0 busy -- (1) timer 1 busy -- -- DSP: SER_MONI.clkdiv (from auto bauder) -- DP(3) not SER_MONI.txok (shows tx back preasure) -- (2) SER_MONI.txact (shows tx activity) -- (1) not SER_MONI.rxok (shows rx back preasure) -- (0) SER_MONI.rxact (shows rx activity) -- library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.serport.all; use work.rblib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.nxcramlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_rlink_n2 is -- top level -- implements nexys2_fusp_aif port ( I_CLK50 : in slbit; -- 50 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n2 switches I_BTN : in slv4; -- n2 buttons O_LED : out slv8; -- n2 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_FLA_CE_N : out slbit; -- flash ce.. (act.low) O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_rlink_n2; architecture syn of sys_tst_rlink_n2 is signal CLK : slbit := '0'; signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv4 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_TST : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv3 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; signal STAT : slv8 := (others=>'0'); constant rbaddr_hio : slv8 := "11000000"; -- 110000xx begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; RESET <= '0'; -- so far not used DCM : dcm_sfs generic map ( CLKFX_DIVIDE => sys_conf_clkfx_divide, CLKFX_MULTIPLY => sys_conf_clkfx_multiply, CLKIN_PERIOD => 20.0) port map ( CLKIN => I_CLK50, CLKFX => CLK, LOCKED => open ); CLKDIV : clkdivce generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC ); IOB_RS232 : bp_rs232_2l4l_iob port map ( CLK => CLK, RESET => '0', SEL => SWI(0), RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); HIO : sn_humanio_rbus generic map ( DEBOUNCE => sys_conf_hio_debounce, RB_ADDR => rbaddr_hio) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_HIO, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RLINK : rlink_sp1c generic map ( ATOWIDTH => 6, ITOWIDTH => 6, CPREF => c_rlink_cpref, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, CDINIT => sys_conf_ser2rri_cdinit) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), ENAESC => SWI(1), RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, SER_MONI => SER_MONI ); RBDTST : entity work.rbd_tst_rlink port map ( CLK => CLK, RESET => RESET, CE_USEC => CE_USEC, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_TST, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RB_SRES_TOP => RB_SRES, RXSD => RXD, RXACT => SER_MONI.rxact, STAT => STAT ); RB_SRES_OR1 : rb_sres_or_2 port map ( RB_SRES_1 => RB_SRES_HIO, RB_SRES_2 => RB_SRES_TST, RB_SRES_OR => RB_SRES ); SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy port map ( O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_FLA_CE_N <= '1'; -- keep Flash memory disabled DSP_DAT <= SER_MONI.abclkdiv; DSP_DP(3) <= not SER_MONI.txok; DSP_DP(2) <= SER_MONI.txact; DSP_DP(1) <= not SER_MONI.rxok; DSP_DP(0) <= SER_MONI.rxact; LED(7) <= SER_MONI.abact; LED(6 downto 2) <= (others=>'0'); LED(1) <= STAT(1); LED(0) <= STAT(0); end syn;
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