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https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [sys_gen/] [tst_rlink/] [rbd_tst_rlink.vhd] - Rev 31
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-- $Id: rbd_tst_rlink.vhd 438 2011-12-11 23:40:52Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: rbd_tst_rlink - syn -- Description: rbus device for tst_rlink -- -- Dependencies: rbus/rbd_tester -- rbus/rbd_bram -- rbus/rbd_rbmon -- rbus/rbd_eyemon -- rbus/rbd_timer -- rbus/rb_sres_or_3 -- rbus/rb_sres_or_4 -- -- Test bench: nexys3/tb/tb_tst_rlink_n3 -- -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment -- 2011-11-11 351 1.0 Initial version (derived from tst_rlink) ------------------------------------------------------------------------------ -- Usage of STAT signal: -- STAT(0): timer 0 busy -- STAT(1): timer 1 busy -- STAT(2:7): unused library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; use work.rbdlib.all; -- ---------------------------------------------------------------------------- entity rbd_tst_rlink is -- rbus device for tst_rlink port ( CLK : in slbit; -- clock RESET : in slbit; -- reset CE_USEC : in slbit; -- usec pulse RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response RB_LAM : out slv16; -- rbus: look at me RB_STAT : out slv3; -- rbus: status flags RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon RXSD : in slbit; -- serport rxsd, for rbd_emon RXACT : in slbit; -- serport rxact, for rbd_emon STAT : out slv8 -- status flags ); end rbd_tst_rlink; architecture syn of rbd_tst_rlink is signal RB_SRES_TEST : rb_sres_type := rb_sres_init; signal RB_SRES_BRAM : rb_sres_type := rb_sres_init; signal RB_SRES_MON : rb_sres_type := rb_sres_init; signal RB_SRES_EMON : rb_sres_type := rb_sres_init; signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init; signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init; signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init; signal RB_LAM_TEST : slv16 := (others=>'0'); signal TIM0_DONE : slbit := '0'; signal TIM0_BUSY : slbit := '0'; signal TIM1_DONE : slbit := '0'; signal TIM1_BUSY : slbit := '0'; constant rbaddr_mon : slv8 := "11111100"; -- 111111xx constant rbaddr_emon : slv8 := "11111000"; -- 111110xx constant rbaddr_bram : slv8 := "11110100"; -- 111101xx constant rbaddr_test : slv8 := "11110000"; -- 111100xx constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001 constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000 begin TEST : rbd_tester generic map ( RB_ADDR => rbaddr_test) port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_TEST, RB_LAM => RB_LAM_TEST, RB_STAT => RB_STAT ); BRAM : rbd_bram generic map ( RB_ADDR => rbaddr_bram) port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_BRAM ); MON : rbd_rbmon generic map ( RB_ADDR => rbaddr_mon, AWIDTH => 9) port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_MON, RB_SRES_SUM => RB_SRES_TOP ); EMON : rbd_eyemon generic map ( RB_ADDR => rbaddr_emon, RDIV => slv(to_unsigned(0,8))) port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_EMON, RXSD => RXSD, RXACT => RXACT ); TIM0 : rbd_timer generic map ( RB_ADDR => rbaddr_tim0) port map ( CLK => CLK, CE_USEC => CE_USEC, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_TIM0, DONE => TIM0_DONE, BUSY => TIM0_BUSY ); TIM1 : rbd_timer generic map ( RB_ADDR => rbaddr_tim1) port map ( CLK => CLK, CE_USEC => CE_USEC, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_TIM1, DONE => TIM1_DONE, BUSY => TIM1_BUSY ); RB_SRES_OR1 : rb_sres_or_3 port map ( RB_SRES_1 => RB_SRES_TEST, RB_SRES_2 => RB_SRES_BRAM, RB_SRES_3 => RB_SRES_MON, RB_SRES_OR => RB_SRES_SUM1 ); RB_SRES_OR : rb_sres_or_4 port map ( RB_SRES_1 => RB_SRES_SUM1, RB_SRES_2 => RB_SRES_EMON, RB_SRES_3 => RB_SRES_TIM0, RB_SRES_4 => RB_SRES_TIM1, RB_SRES_OR => RB_SRES ); RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2); RB_LAM(1) <= TIM1_DONE; RB_LAM(0) <= TIM0_DONE; STAT(0) <= TIM0_BUSY; STAT(1) <= TIM1_BUSY; STAT(7 downto 2) <= (others=>'0'); end syn;
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