Subversion Repositories w11

# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $
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[xst]
INFO:.*Mux is complete : default of case is discarded
INFO:.*You can improve the performance of the multiplier

Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <HIO/R_REGS.swieff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.swi_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <MEM_SRAM.SRAM_CTL/R_REGS.addr0> of sequential type is unconnected

Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'

Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
Input <IB_MREQ.cacc> is never used
Input <IB_MREQ.rmw> is never used
Input <IB_MREQ.din<\d*:\d*>> is never used
Input <IB_MREQ.din<\d*>> is never used
Input <IB_MREQ.racc> is never used
Input <IB_MREQ.be0> is never used
Input <IB_MREQ.be1> is never used
Input <IB_MREQ.din> is never used
Input <IB_MREQ.re> is never used
Input <IB_MREQ.we> is never used
Input <IB_MREQ.addr<\d*:\d*>> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.init> is never used
Input <RB_MREQ.din<\d*:\d*>> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used

Signal <R_VMSTAT.trap_ysv> is assigned but never used
Signal <R_VMSTAT.trap_mmu> is assigned but never used
Signal <R_VMSTAT.ack> is assigned but never used
Signal <R_IDSTAT.is_res> is assigned but never used
Signal <R_IDSTAT.fork_srcr> is assigned but never used
Signal <R_IDSTAT.fork_op> is assigned but never used
Signal <R_IDSTAT.force_srcsp> is assigned but never used
Signal <R_IDSTAT.do_pref_dec> is assigned but never used
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT.do_fork_opg> is assigned but never used
Signal <R_IDSTAT.do_fork_op> is assigned but never used
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used

Signal <DM_STAT_VM.ibsres.dout> is assigned but never used
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used
Signal <DM_STAT_DP.psw.tflag> is assigned but never used
Signal <DM_STAT_DP.psw.rset> is assigned but never used
Signal <DM_STAT_DP.psw.pmode> is assigned but never used
Signal <DM_STAT_DP.psw.cc> is assigned but never used
Signal <DM_STAT_DP.pc> is assigned but never used
Signal <DM_STAT_DP.ireg_we> is assigned but never used
Signal <DM_STAT_DP.ireg> is assigned but never used
Signal <DM_STAT_DP.gpr_we> is assigned but never used
Signal <DM_STAT_DP.gpr_mode> is assigned but never used
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used
Signal <DM_STAT_DP.gpr_adst> is assigned but never used
Signal <DM_STAT_DP.dtmp> is assigned but never used
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used

Signal <IIST_MREQ.lock> is assigned but never used
Signal <IIST_MREQ.boot> is assigned but never used

Signal <EI_ACK_RL11> is assigned but never used
Signal <EI_ACK_KW11P> is assigned but never used
Signal <EI_ACK_DZ11TX> is assigned but never used
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used

Signal <SIZE<\d*:\d*>> is assigned but never used
Signal <SWI<\d*:\d*>> is assigned but never used
Signal <BTN> is assigned but never used

FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.memdi_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_n2> is equivalent

FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.cntdly_\d*> has a constant value of 0
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value
FF/Latch <MEM_SRAM.SRAM_CTL/IOB_MEM_ADDRH/R_DO_\d*> has a constant value of 0
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0

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[tra]
INFO:.*TNM.*used in period specification.*was traced into DCM_SP

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[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
There is a dangling output parity pin
INFO:.*

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[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
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[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete
There is a dangling output parity pin
INFO:.*To achieve optimal frequency synthesis performance