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# $Id: tb_rlink_serport_stim.dat 351 2010-12-30 21:50:54Z mueller $
#
#  Revision History: 
# Date         Rev Version  Comment
# 2010-12-29   351   1.0.1  use new rbd_tester addr 111100xx (from 111101xx)
# 2010-12-26   348   1.0    Initial version (Test 3 from tb_rlink_stim.dat)
#
#---------------------------------------
# rbus address mapping
#   11110000   rbd_tester cntl
#   11110001   rbd_tester data
#   11110010   rbd_tester fifo
#   11110011   rbd_tester attn
#
.rlmon 0
.rbmon 1
#
C -----------------------------------------------------------------------------
C Test 1: wreg(data)
C   data := 0011001111001100
C   ==> shows that rlink can write a register
C
C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
C       rx: sop - cmd(010) stat crc - eop
#
rxsop 
rxcs   00001010 00000000
rxeop 
#
txsop 
txcad  00001010 11110001 0011001111001100
txeop 
#
.iowt 10
#
C -----------------------------------------------------------------------------
C Test 2: rreg(data)
C   data -> 0011001111001100
C   ==> shows that rlink can read back a register
C
C rreg: tx: sop - cmd(00001,000) addr(0001) ccrc - eop
C       rx: sop - cmd(000) dl dh stat crc - eop
#
rxsop 
rxcds  00001000          0011001111001100 00000000
rxeop 
#
txsop 
txca   00001000 11110001
txeop 
#
.iowt 10
#
C -----------------------------------------------------------------------------
C Test 3: Test comma escapes
C         Assumes CPREF=1000, covers 11111111:10000111 and 10001101:10010000
C
C   data := 1000000011111111      <idle>,...
C   data -> 1000000011111111
C   data := 1000001010000001      <eop> ,<sop>
C   data -> 1000001010000001
C   data := 1000010010000011      <attn>,<nak>
C   data -> 1000010010000011
C   data := 1000011010000101      6,5
C   data -> 1000011010000101
C   data := 1000100010000111      8,7
C   data -> 1000100010000111
C   data := 1000111010001101      14,13
C   data -> 1000111010001101
C   data := 1001000010001111      ..,<esc>
C   data -> 1001000010001111
C
C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(00010,000) addr(0001) ccrc
C wreg: tx:     - cmd(00011,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(00100,000) addr(0001) ccrc
C wreg: tx:     - cmd(00101,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(00110,000) addr(0001) ccrc
C wreg: tx:     - cmd(00111,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(01000,000) addr(0001) ccrc
C wreg: tx:     - cmd(01001,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(01010,000) addr(0001) ccrc
C wreg: tx:     - cmd(01011,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(01100,000) addr(0001) ccrc
C wreg: tx:     - cmd(01101,010) addr(0001) dl dh ccrc
C rreg: tx:     - cmd(01110,000) addr(0001) ccrc
C       tx:     - eop
C       rx: sop - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - eop
#
rxsop 
rxcs   00001010 00000000
rxcds  00010000          1000000011111111 00000000
rxcs   00011010 00000000
rxcds  00100000          1000001010000001 00000000
rxcs   00101010 00000000
rxcds  00110000          1000010010000011 00000000
rxcs   00111010 00000000
rxcds  01000000          1000011010000101 00000000
rxcs   01001010 00000000
rxcds  01010000          1000100010000111 00000000
rxcs   01011010 00000000
rxcds  01100000          1000111010001101 00000000
rxcs   01101010 00000000
rxcds  01110000          1001000010001111 00000000
rxeop 
#
txsop 
txcad  00001010 11110001 1000000011111111
txca   00010000 11110001 
txcad  00011010 11110001 1000001010000001
txca   00100000 11110001 
txcad  00101010 11110001 1000010010000011
txca   00110000 11110001 
txcad  00111010 11110001 1000011010000101
txca   01000000 11110001 
txcad  01001010 11110001 1000100010000111
txca   01010000 11110001 
txcad  01011010 11110001 1000111010001101
txca   01100000 11110001 
txcad  01101010 11110001 1001000010001111
txca   01110000 11110001 
txeop 
#
.iowt 10
#
C -----------------------------------------------------------------------------
C Test 4: Test RTS throttling via wreg/rreg
C         Note: RTS_N response is *not* selfchecking, look into log and check
C               for 'RTS_N' lines.
C
C   init (11111110:0000000000001000)  fena(0),fwth(0),fdly(0),rtsoff(1),rtson(0)
C   fifo := 1000000010000000
C   fifo := 1000000010000001
C   fifo := 1000000010000010
C   fifo := 1000000010000011
C   fifo := 1000000110000000
C   fifo := 1000000110000001
C   fifo := 1000000110000010
C   fifo := 1000000110000011
C   fifo -> 8 read (will produce escapes for dl and dh, thus slow down a bit)
C
C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc
C wreg: tx:     - cmd(00001,010) addr(0010) dl dh ccrc
C wreg:           ....
C wreg: tx:     - cmd(01000,010) addr(0010) dl dh ccrc
C rreg: tx:     - cmd(10001,000) addr(0010) ccrc
C                 ....
C rreg: tx:     - cmd(11000,000) addr(0010) ccrc
C       tx:     - eop
C       rx: sop - cmd(110) stat crc
C       rx:     - cmd(010) stat crc
C                 ...
C       rx:     - cmd(010) stat crc
C       rx:     - cmd(000) dl dh stat crc
C                 ...
C       rx:     - cmd(000) dl dh stat crc
C       rx:     - eop
C
#
rxsop 
rxcs   11110110 00000000
rxcs   00001010 00000000
rxcs   00010010 00000000
rxcs   00011010 00000000
rxcs   00100010 00000000
rxcs   00101010 00000000
rxcs   00110010 00000000
rxcs   00111010 00000000
rxcs   01000010 00000000
rxcds  10001000          1000000010000000 00000000
rxcds  10010000          1000000010000001 00000000
rxcds  10011000          1000000010000010 00000000
rxcds  10100000          1000000010000011 00000000
rxcds  10101000          1000000110000000 00000000
rxcds  10110000          1000000110000001 00000000
rxcds  10111000          1000000110000010 00000000
rxcds  11000000          1000000110000011 00000000
rxeop 
#
txsop 
txcad  11110110 11111110 0000000000001000
txcad  00001010 11110010 1000000010000000
txcad  00010010 11110010 1000000010000001
txcad  00011010 11110010 1000000010000010
txcad  00100010 11110010 1000000010000011
txcad  00101010 11110010 1000000110000000
txcad  00110010 11110010 1000000110000001
txcad  00111010 11110010 1000000110000010
txcad  01000010 11110010 1000000110000011
txca   10001000 11110010 
txca   10010000 11110010 
txca   10011000 11110010 
txca   10100000 11110010 
txca   10101000 11110010 
txca   10110000 11110010 
txca   10111000 11110010 
txca   11000000 11110010 
txeop 
#
.iowt 10
#
C -----------------------------------------------------------------------------
C Test 5: Test RTS flush pulse
C         Note: RTS_N response is *not* selfchecking, look into log and check
C               for 'RTS_N' lines.
C
C 1a. setup width=1, delay=1
C
C   init (11111110:0001001001111110)  fena(1),fwth(1),fdly(1),rtsoff(7),rtson(6)
C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
#
rxsop 
rxcs   11110110 00000000
rxeop 
txsop 
txcad  11110110 11111110 0001001001111110
txeop 
.iowt 10
.wait 50
C
C 1b. test with wreg sequence
C   data := 0000000000000001
C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
C       rx: sop - cmd(010) stat crc - eop
C
#
rxsop 
rxcs   00001010 00000000
rxeop 
txsop 
txcad  00001010 11110001 0000000000000001
txeop 
.iowt 10
.wait 50
C
C 2a. setup width=3, delay=1
C
C   init (11111110:0001011001111110)  fena(1),fwth(3),fdly(1),rtsoff(7),rtson(6)
C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
#
rxsop 
rxcs   11110110 00000000
rxeop 
txsop 
txcad  11110110 11111110 0001011001111110
txeop 
.iowt 10
.wait 50
C
C 2b. test with wreg sequence
C   data := 0000000000000001
C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
C       rx: sop - cmd(010) stat crc - eop
#
rxsop 
rxcs   00001010 00000000
rxeop 
txsop 
txcad  00001010 11110001 0000000000000001
txeop 
.iowt 10
.wait 50
#
C
C 3a. setup width=7, delay=7
C
C   init (11111110:0001111111111110)  fena(1),fwth(7),fdly(7),rtsoff(7),rtson(6)
C init: tx: sop - cmd(11110,110) addr(----) dl dh ccrc - eop
#
rxsop 
rxcs   11110110 00000000
rxeop 
txsop 
txcad  11110110 11111110 0001111111111110
txeop 
.iowt 10
.wait 50
C
C 3b. test with wreg sequence
C   data := 0000000000000001
C wreg: tx: sop - cmd(00001,010) addr(0001) dl dh ccrc - eop
C       rx: sop - cmd(010) stat crc - eop
#
rxsop 
rxcs   00001010 00000000
rxeop 
txsop 
txcad  00001010 11110001 0000000000000001
txeop 
.iowt 10
.wait 50
#
#==============================================================================
#
C -----------------------------------------------------------------------------
C Run down and Finish
.iowt 10
.wait 100