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[/] [w11/] [tags/] [w11a_V0.61/] [rtl/] [bplib/] [nexys2/] [nexys2_time_fx2_ic.ucf] - Rev 32
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## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##
## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a
## clock capable pin -> not ok when FX2 uses internal clock. So allow par
## to route from a 'normal' pin to a clock net. Not nice, compromizes the
## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok).
## In practice IFCLK to pad times are quite similar on nexys2 and nexys3...
NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
##
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
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