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# $Id: sys_tst_rlink_n2.mfset 440 2011-12-18 20:08:09Z mueller $
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[xst]
INFO:.*Mux is complete : default of case is discarded

Node <HIO/R_REGS.swieff_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-5]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-5]> of sequential type is unconnected

Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c'

Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <CE_USEC> is never used

Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SWI<7:2>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <BTN> is assigned but never used

FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent

FF/Latch <R_REGS.ledin_2> has a constant value of 0
FF/Latch <R_REGS.ucnt_6> has a constant value of 0

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[tra]

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[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
INFO:.*

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[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
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[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete